experiments2/part_sig_add.py

   1 from nmigen.cli import rtlil
   2 from test_partsig import TestAddMod2
   3 import subprocess
   4 import os
   5 from nmigen import Signal
   6
   7 def test():
   8     width = 16
   9     pmask = Signal(3)  # divide into 4-bits
  10     module = TestAddMod2(width, pmask)
  11     sim = create_ilang(module,
  12                                [pmask,
  13                                 module.a.sig,
  14                                 module.b.sig,
  15                                 module.add_output,
  16                                 module.ls_output,
  17                                 module.sub_output,
  18                                 module.eq_output,
  19                                 module.gt_output,
  20                                 module.ge_output,
  21                                 module.ne_output,
  22                                 module.lt_output,
  23                                 module.le_output,
  24                                 module.mux_sel,
  25                                 module.mux_out,
  26                                 module.carry_in,
  27                                 module.add_carry_out,
  28                                 module.sub_carry_out,
  29                                 module.neg_output,
  30                                ],
  31                                "part_sig_add")
  32
  33 def create_ilang(dut, ports, test_name):
  34     vl = rtlil.convert(dut, name=test_name, ports=ports)
  35     with open("%s.il" % test_name, "w") as f:
  36         f.write(vl)
  37
  38 if __name__ == "__main__":
  39     test()