experiments2/test_partsig.py

   1 #!/usr/bin/env python3
   2 # SPDX-License-Identifier: LGPL-2.1-or-later
   3 # See Notices.txt for copyright information
   4
   5 from nmigen import Signal, Module, Elaboratable
   6 from nmigen.back.pysim import Simulator, Delay
   7 from nmigen.cli import rtlil
   8
   9 from ieee754.part.partsig import PartitionedSignal
  10 from ieee754.part_mux.part_mux import PMux
  11
  12
  13 # XXX this is for coriolis2 experimentation
  14 class TestLS(Elaboratable):
  15     def __init__(self, width, partpoints):
  16         self.partpoints = partpoints
  17         self.a = PartitionedSignal(partpoints, width, name="a")
  18         self.b = PartitionedSignal(partpoints, width, name="b")
  19         self.ls_output = Signal(width) # left shift
  20         self.dummy_output = Signal(width) # left shift
  21
  22     def elaborate(self, platform):
  23         m = Module()
  24         comb = m.d.comb
  25         sync = m.d.sync
  26         self.a.set_module(m)
  27         self.b.set_module(m)
  28         # left shift
  29         sync += self.dummy_output.eq(self.b.sig) # stops sigs being ignored
  30         sync += self.ls_output.eq(self.a << self.b)
  31         ppts = self.partpoints
  32
  33         return m
  34
  35     def ports(self):
  36         return [self.a.sig, self.b.sig,
  37                 self.ls_output,
  38                 self.dummy_output]
  39
  40
  41 # XXX this is for coriolis2 experimentation
  42 class TestAddMod2(Elaboratable):
  43     def __init__(self, width, partpoints):
  44         self.partpoints = partpoints
  45         self.a = PartitionedSignal(partpoints, width, name="a")
  46         self.b = PartitionedSignal(partpoints, width, name="b")
  47         self.add_output = Signal(width)
  48         self.ls_output = Signal(width) # left shift
  49         self.sub_output = Signal(width)
  50         self.carry_in = Signal(len(partpoints)+1)
  51         self.add_carry_out = Signal(len(partpoints)+1)
  52         self.sub_carry_out = Signal(len(partpoints)+1)
  53         self.neg_output = Signal(width)
  54
  55     def elaborate(self, platform):
  56         m = Module()
  57         comb = m.d.comb
  58         sync = m.d.sync
  59         self.a.set_module(m)
  60         self.b.set_module(m)
  61         # add
  62         add_out, add_carry = self.a.add_op(self.a, self.b,
  63                                            self.carry_in)
  64         sync += self.add_output.eq(add_out)
  65         sync += self.add_carry_out.eq(add_carry)
  66         # sub
  67         sub_out, sub_carry = self.a.sub_op(self.a, self.b,
  68                                            self.carry_in)
  69         sync += self.sub_output.eq(sub_out)
  70         sync += self.sub_carry_out.eq(sub_carry)
  71         # neg
  72         sync += self.neg_output.eq(-self.a)
  73         # left shift
  74         sync += self.ls_output.eq(self.a << self.b)
  75         ppts = self.partpoints
  76
  77         return m
  78
  79     def ports(self):
  80         return [self.a.sig, self.b.sig,
  81                 self.add_output,
  82                 self.ls_output,
  83                 self.sub_output,
  84                 self.carry_in,
  85                 self.add_carry_out,
  86                 self.sub_carry_out,
  87                 self.neg_output]
  88
  89