experiments9/freepdk_c4m45/Makefile

   1             # use git submodule version of c4m-pdk-freepdk45
   2             # remember to do "git submodule update --init --remote
   3             PDKMASTER_TOP = $(shell pwd)/../../c4m-pdk-freepdk45
   4         LOGICAL_SYNTHESIS = Yosys
   5        PHYSICAL_SYNTHESIS = Coriolis
   6                DESIGN_KIT = FreePDK_C4M45
   7              YOSYS_FLATTEN = No
   8 #            YOSYS_SET_TOP = Yes
   9                     CHIP  = chip
  10                     CORE  = ls180
  11             USE_CLOCKTREE = Yes
  12                 USE_DEBUG = No
  13                   RM_CHIP = Yes
  14                 VST_FLAGS = --vst-uniquify-uppercase
  15
  16                  #NETLISTS = $(shell cat cells.lst)
  17                  NETLISTS = ls180
  18 #            YOSYS_FLATTEN = $(shell cat flatten.lst)
  19
  20  include ./mk/design-flow.mk
  21
  22 chip_r.vst: ls180.vst
  23         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  24
  25 chip_r.ap: chip_r.vst
  26
  27 pinmux:
  28         (cd coriolis2 && python ../../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  29         ln -f -s ../../../pinmux/src/parse.py coriolis2/pinparse.py
  30         ln -f -s coriolis2/ls180 ls180
  31
  32 blif:      ls180.blif
  33 vst:       ls180.vst
  34
  35 lvx:       lvx-chip_r
  36 druc:      druc-chip_r
  37 dreal:     dreal-chip_r
  38 flatph:     flatph-chip_r
  39 view:      cgt-chip_r
  40
  41 layout:    chip_r.ap
  42 gds:       chip_r.gds
  43 gds_flat:  chip_r_flat.gds
  44 cif:       chip_r.cif
  45
  46
  47 view:      cgt-chip_r
  48 sim:       asimut-ls180_r