2 #include "hwacha_xcpt.h"
5 void ct_state_t::reset()
18 void ut_state_t::reset()
25 void hwacha_t::reset()
28 for (int i
=0; i
<max_uts
; i
++)
32 static reg_t
custom(processor_t
* p
, insn_t insn
, reg_t pc
)
34 hwacha_t
* h
= static_cast<hwacha_t
*>(p
->get_extension());
40 #define DECLARE_INSN(name, match, mask) \
41 extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
42 if ((insn.bits() & mask) == match) { \
43 npc = hwacha_##name(p, insn, pc); \
46 #include "opcodes_hwacha.h"
49 catch (trap_instruction_access_fault
& t
)
51 h
->take_exception(HWACHA_CAUSE_VF_FAULT_FETCH
, h
->get_ct_state()->vf_pc
);
53 catch (trap_load_address_misaligned
& t
)
55 h
->take_exception(HWACHA_CAUSE_MISALIGNED_LOAD
, t
.get_badvaddr());
57 catch (trap_store_address_misaligned
& t
)
59 h
->take_exception(HWACHA_CAUSE_MISALIGNED_STORE
, t
.get_badvaddr());
61 catch (trap_load_access_fault
& t
)
63 h
->take_exception(HWACHA_CAUSE_FAULT_LOAD
, t
.get_badvaddr());
65 catch (trap_store_access_fault
& t
)
67 h
->take_exception(HWACHA_CAUSE_FAULT_STORE
, t
.get_badvaddr());
71 h
->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION
, insn
.bits());
76 std::vector
<insn_desc_t
> hwacha_t::get_instructions()
78 std::vector
<insn_desc_t
> insns
;
79 insns
.push_back((insn_desc_t
){0x0b, 0x7f, &::illegal_instruction
, custom
});
80 insns
.push_back((insn_desc_t
){0x2b, 0x7f, &::illegal_instruction
, custom
});
81 insns
.push_back((insn_desc_t
){0x5b, 0x7f, &::illegal_instruction
, custom
});
82 insns
.push_back((insn_desc_t
){0x7b, 0x7f, &::illegal_instruction
, custom
});
86 bool hwacha_t::vf_active()
88 for (uint32_t i
=0; i
<get_ct_state()->vl
; i
++) {
89 if (get_ut_state(i
)->run
)
95 void hwacha_t::take_exception(reg_t cause
, reg_t aux
)
97 get_ct_state()->cause
= cause
;
98 get_ct_state()->aux
= aux
;
100 if (!(p
->get_state()->sr
& SR_EI
))
101 throw std::logic_error("hwacha exception posted, but SR_EI bit not set!");
102 throw std::logic_error("hwacha exception posted, but IM[COP] bit not set!");