Move half precision instructions, add vfmsv, vfmvv
[riscv-isa-sim.git] / hwacha / insn_template_hwacha.cc
1 // See LICENSE for license details.
2
3 #include "config.h"
4 #include "processor.h"
5 #include "mmu.h"
6 #include "hwacha.h"
7 #include "decode_hwacha.h"
8 #include "encodings_hwacha.h"
9 #include "rocc.h"
10 #include <assert.h>
11
12 reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
13 {
14 int xprlen = 64;
15 reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
16 hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
17 rocc_insn_union_t u;
18 u.i = insn;
19 reg_t xs1 = u.r.xs1 ? RS1 : -1;
20 reg_t xs2 = u.r.xs2 ? RS2 : -1;
21 reg_t xd = -1;
22 #include "insns/NAME.h"
23 if (u.r.xd) WRITE_RD(xd);
24 return npc;
25 }