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HEAD
Move half precision instructions, add vfmsv, vfmvv
[riscv-isa-sim.git]
/
hwacha
/
insns_ut
/
ut_fcvt_w_h.h
1
require_fp
;
2
softfloat_roundingMode
=
RM
;
3
WRITE_RD
(
sext32
(
f32_to_i32
(
HFRS1
,
RM
,
true
)));
4
set_fp_exceptions
;