Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEAD

[riscv-isa-sim.git] / hwacha / insns_ut_half / ut_fcvt_h_l.h

require_xpr64;
require_fp;
softfloat_roundingMode = RM;
WRITE_HFRD(i64_to_f32(RS1));
set_fp_exceptions;