1 #define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
3 #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
4 (reg0 | (reg1<<8) | (reg2<<8) | \
5 (shape0<<24) | (shape0<<26) | (shape0<<28))
7 #define SV_SHAPE_PERM_XYZ 0
8 #define SV_SHAPE_PERM_XZY 1
9 #define SV_SHAPE_PERM_YXZ 2
10 #define SV_SHAPE_PERM_YZX 3
11 #define SV_SHAPE_PERM_ZXY 4
12 #define SV_SHAPE_PERM_ZYX 5
14 #define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \
15 ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \
16 ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) )
19 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
20 (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
21 #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
22 (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
24 #define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
25 li x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \
28 #define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \
29 li x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
32 // series of macros that set one, two or three register (or predicate)
33 // key-value table entries that alter the behaviour of the registers
34 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
35 li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
38 #define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \
39 li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
42 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
43 li x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
46 #define SET_SV_2CSRS( c1, c2 ) \
47 li x1, c1 | ((c2)<<16U); \
50 #define SET_SV_3CSRS( c1, c2 , c3 ) \
51 li x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
54 #define SET_SV_2PREDCSRS( c1, c2 ) \
55 li x1, c1 | ((c2)<<16U); \
58 // clears the 2 CSRs set above
59 #define CLR_SV_CSRS( ) csrrwi x0, 0x4c0, 0xf;
60 #define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0
62 // set maximum vector length.
63 #define SET_SV_MVL( val ) csrrwi x0, 0x4f1, (val-1)
65 // set actual vector length: normally that would
66 // be vl = xN = min(mvl, min(vl, xN) however we
68 #define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1)
70 #define SV_LD_DATA( reg, from, offs ) \
74 #define SV_LDD_DATA( reg, from, offs ) \
78 #define SV_FLD_DATA( reg, from, offs ) \
82 #define SV_FLW_DATA( reg, from, offs ) \
86 #define TEST_SV_IMMW( reg, imm ) \
87 li t6, MASK_XLEN(imm) ; \
90 #define TEST_SV_IMM( reg, imm ) \
91 li t6, ((imm) & 0xffffffffffffffff); \
94 #define TEST_SV_FD( flags, freg, from, offs ) \
103 #define TEST_SV_FW( flags, freg, from, offs ) \
112 // Loads the source registers using load_instruction from testdata with a spacing of elwidth
113 #define SV_LOAD_FORMAT(load_instruction, testdata, elwidth) \
114 load_instruction x12, (testdata); \
115 load_instruction x13, (testdata+elwidth); \
116 load_instruction x14, (testdata+elwidth*2); \
117 load_instruction x15, (testdata+elwidth*3); \
118 load_instruction x16, (testdata+elwidth*4); \
119 load_instruction x17, (testdata+elwidth*5); \
121 // Loads the source registers using load_instruction from testdata with a spacing of elwidth and offset
122 #define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset) \
123 load_instruction( x12, testdata, offset); \
124 load_instruction( x13, testdata+elwidth, offset); \
125 load_instruction( x14, testdata+elwidth*2, offset); \
126 load_instruction( x15, testdata+elwidth*3, offset); \
127 load_instruction( x16, testdata+elwidth*4, offset); \
128 load_instruction( x17, testdata+elwidth*5, offset); \
130 // This should be used in all cases where three parameters are formed with an instruction
131 // IE addw x28, x15, x12 will be generated
132 #define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, offset, \
133 vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
134 expect1, expect2, expect3 ) \
136 SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset), \
137 vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
138 expect1, expect2, expect3, code x28, x15, x12) \
140 // This should be used in all cases where two parameters are formed with an instruction
141 // IE ld x28 (0)x12 will be generated
142 #define SV_ELWIDTH_TEST_LOAD(code, load_instruction, testdata, elwidth, \
143 vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
144 expect1, expect2, expect3 ) \
146 SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT(load_instruction, testdata, elwidth), \
147 vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
148 expect1, expect2, expect3, code x28, 0(x12)) \
150 // This should not be accessed directly. It is meant to be called through higher level macros.
152 // 1. The 'load_type' parameter should be a SV_LOAD_FORMAT_* macro to
153 // generate loading instructions.
154 // 2. The 'code' parameter should take on the form of the instruction being tested
155 // IE addw x28, x15, x12.
156 // Note: The destination register is always 28. The source registers are always 12 and 15
157 #define SV_ELWIDTH_TEST_INNER(load_type, vl, wid1, wid2, wid3, \
158 isvec1, isvec2, isvec3, \
159 expect1, expect2, expect3, code... ) \
162 li x28, 0xa5a5a5a5a5a5a5a5; \
163 li x29, 0xa5a5a5a5a5a5a5a5; \
164 li x30, 0xa5a5a5a5a5a5a5a5; \
167 SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \
168 SV_REG_CSR( 1, 12, wid2, 12, isvec2), \
169 SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \
178 TEST_SV_IMM( x28, expect1 ); \
179 TEST_SV_IMM( x29, expect2 ); \
180 TEST_SV_IMM( x30, expect3 ); \
186 #define SV_W_DEFAULT_EXPECT 0xa5a5a5a5a5a5a5a5