beef up rv32si tests
[riscv-tests.git] / isa / rv32si / ipi_zscale.S
1 #*****************************************************************************
2 # ipi.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test ipi interrupt.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32S
12 RVTEST_CODE_BEGIN
13
14 la t0, evec
15 csrw evec, t0
16
17 csrw clear_ipi, x0
18 li t1, 1<<21
19 csrs status, t1 # turn on timer IRQ 5
20 csrsi status, 4 # enable interrupts
21
22 li t1,1
23 csrw send_ipi, t1
24
25 li TESTNUM, 2
26 li a0,1000
27 loop:
28 div x0, x0, x0
29 addi a0, a0, -1
30 bne a0, x0, loop
31 j fail # assumption is that you will get an ipi before this loop ends
32
33 TEST_PASSFAIL
34
35 evec:
36 li t1, 0x80000000|IRQ_IPI
37 csrr t0, cause
38 bne t0, t1, fail
39 j pass
40
41 RVTEST_CODE_END
42
43 .data
44 RVTEST_DATA_BEGIN
45
46 TEST_DATA
47
48 RVTEST_DATA_END