isa/rv64mi/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   .align 3
  17   auipc s0, 0
  18
  19   # indicate it's a load test
  20   li s1, CAUSE_MISALIGNED_LOAD
  21
  22 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
  23   li TESTNUM, testnum; \
  24   insn x0, offset(base); \
  25   j fail \
  26
  27   MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
  28   MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
  29   MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
  30   MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
  31   MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
  32
  33 #ifdef __riscv64
  34   MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
  35   MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
  36   MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
  37
  38   MISALIGNED_LDST_TEST(10, ld, s0, 1)
  39   MISALIGNED_LDST_TEST(11, ld, s0, 2)
  40   MISALIGNED_LDST_TEST(12, ld, s0, 3)
  41   MISALIGNED_LDST_TEST(13, ld, s0, 4)
  42   MISALIGNED_LDST_TEST(14, ld, s0, 5)
  43   MISALIGNED_LDST_TEST(15, ld, s0, 6)
  44   MISALIGNED_LDST_TEST(16, ld, s0, 7)
  45 #endif
  46
  47   # indicate it's a store test
  48   li s1, CAUSE_MISALIGNED_STORE
  49
  50   MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
  51   MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
  52   MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
  53   MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
  54
  55 #ifdef __riscv64
  56   MISALIGNED_LDST_TEST(26, sd, s0, 1)
  57   MISALIGNED_LDST_TEST(27, sd, s0, 2)
  58   MISALIGNED_LDST_TEST(28, sd, s0, 3)
  59   MISALIGNED_LDST_TEST(29, sd, s0, 4)
  60   MISALIGNED_LDST_TEST(30, sd, s0, 5)
  61   MISALIGNED_LDST_TEST(31, sd, s0, 6)
  62   MISALIGNED_LDST_TEST(32, sd, s0, 7)
  63 #endif
  64
  65   TEST_PASSFAIL
  66
  67   .align 3
  68 mtvec_handler:
  69   csrr t0, mcause
  70   bne t0, s1, fail
  71
  72   csrr t0, mepc
  73   addi t0, t0, 8
  74   csrw mepc, t0
  75   sret
  76
  77 RVTEST_CODE_END
  78
  79   .data
  80 RVTEST_DATA_BEGIN
  81
  82   TEST_DATA
  83
  84 RVTEST_DATA_END