1 # See LICENSE for license details.
3 #*****************************************************************************
5 #-----------------------------------------------------------------------------
7 # Test VM referenced and dirty bits.
10 #include "riscv_test.h"
11 #include "test_macros.h"
16 # Turn on VM with superpage identity mapping
17 li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
19 srl a1, a1, RISCV_PGSHIFT
22 srl a2, a2, RISCV_PGSHIFT
26 li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
30 la a1, stvec_handler - DRAM_BASE
35 # Try a faulting store to make sure dirty bit is not set
45 # Try a non-faulting store to make sure dirty bit is set
48 # Make sure D bit is set
61 add t0, t0, -CAUSE_FAULT_STORE
66 # Make sure D bit is clear
79 # The implementation doesn't appear to set D bits in HW. Skip the test,
80 # after making sure the D bit is clear.
98 page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_A
101 page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W | PTE_A