1 -- SPBlock_512W64B8W simulation model
3 use ieee.std_logic_1164.all;
4 use ieee.numeric_std.all;
6 entity SPBlock_512W64B8W is
9 A: in std_logic_vector(8 downto 0);
10 D: in std_logic_vector(63 downto 0);
11 Q: out std_logic_vector(63 downto 0);
12 -- Width of WE determines the write granularity
13 WE: in std_logic_vector(7 downto 0)
15 end entity SPBlock_512W64B8W;
17 architecture rtl of SPBlock_512W64B8W is
18 constant WORDS: integer := 512;
19 constant WEBITS: integer := WE'length;
20 constant WEWORDBITS: integer := 8;
21 type word is array (WEBITS - 1 downto 0) of std_logic_vector(WEWORDBITS - 1 downto 0);
22 type ram_type is array (0 to WORDS - 1) of word;
25 signal A_hold: std_logic_vector(A'range);
28 signal addr_hold: integer;
30 addr <= to_integer(unsigned(A));
31 addr_hold <= to_integer(unsigned(A_hold));
35 if (rising_edge(CLK)) then
37 for weword in 0 to WEBITS - 1 loop
38 if WE(weword) = '1' then
40 RAM(addr)(weword) <= D((weword + 1)*WEWORDBITS - 1 downto weword*WEWORDBITS);
46 read: for weword in 0 to WE'length - 1 generate
48 Q((weword + 1)*WEWORDBITS - 1 downto weword*WEWORDBITS) <= RAM(addr_hold)(weword);