adding edited versions of chip/corona
[soc-cocotb-sim.git] / ls180 / post_pnr / chip_corona / chip.vhd
1
2 -- =======================================================================
3 -- Coriolis Structural VHDL Driver
4 -- Generated on Apr 10, 2021, 13:40
5 --
6 -- To be interoperable with Alliance, it uses it's special VHDL subset.
7 -- ("man vhdl" under Alliance for more informations)
8 -- =======================================================================
9
10 LIBRARY IEEE;
11 USE IEEE.std_logic_1164.ALL;
12 USE IEEE.numeric_std.ALL;
13
14 entity chip is
15 port ( eint_0 : inout std_logic
16 ; eint_1 : inout std_logic
17 ; eint_2 : inout std_logic
18 ; gpio_10 : inout std_logic
19 ; gpio_11 : inout std_logic
20 ; gpio_12 : inout std_logic
21 ; gpio_13 : inout std_logic
22 ; gpio_14 : inout std_logic
23 ; gpio_15 : inout std_logic
24 ; i2c_sda : inout std_logic
25 ; jtag_tck : inout std_logic
26 ; jtag_tdi : inout std_logic
27 ; jtag_tms : inout std_logic
28 ; sdram_dq_10 : inout std_logic
29 ; sdram_dq_11 : inout std_logic
30 ; sdram_dq_12 : inout std_logic
31 ; sdram_dq_13 : inout std_logic
32 ; sdram_dq_14 : inout std_logic
33 ; sdram_dq_15 : inout std_logic
34 ; spimaster_miso : inout std_logic
35 ; sys_clk : inout std_logic
36 ; sys_rst : inout std_logic
37 ; uart_rx : inout std_logic
38 ; uart_tx : inout std_logic
39 ; nc : inout std_logic_vector(39 downto 0)
40 ; gpio_0 : inout std_logic
41 ; gpio_1 : inout std_logic
42 ; gpio_2 : inout std_logic
43 ; gpio_3 : inout std_logic
44 ; gpio_4 : inout std_logic
45 ; gpio_5 : inout std_logic
46 ; gpio_6 : inout std_logic
47 ; gpio_7 : inout std_logic
48 ; gpio_8 : inout std_logic
49 ; gpio_9 : inout std_logic
50 ; i2c_scl : inout std_logic
51 ; jtag_tdo : inout std_logic
52 ; sdram_cas_n : inout std_logic
53 ; sdram_cke : inout std_logic
54 ; sdram_clock : inout std_logic
55 ; sdram_cs_n : inout std_logic
56 ; sdram_dq_0 : inout std_logic
57 ; sdram_dq_1 : inout std_logic
58 ; sdram_dq_2 : inout std_logic
59 ; sdram_dq_3 : inout std_logic
60 ; sdram_dq_4 : inout std_logic
61 ; sdram_dq_5 : inout std_logic
62 ; sdram_dq_6 : inout std_logic
63 ; sdram_dq_7 : inout std_logic
64 ; sdram_dq_8 : inout std_logic
65 ; sdram_dq_9 : inout std_logic
66 ; sdram_ras_n : inout std_logic
67 ; sdram_we_n : inout std_logic
68 ; spimaster_clk : inout std_logic
69 ; spimaster_cs_n : inout std_logic
70 ; spimaster_mosi : inout std_logic
71 ; sdram_ba : inout std_logic_vector(1 downto 0)
72 ; sdram_dm : inout std_logic_vector(1 downto 0)
73 ; sdram_a : inout std_logic_vector(12 downto 0)
74 ; iovdd : in bit
75 ; iovss : in bit
76 ; vdd : in bit
77 ; vss : in bit
78 );
79 end chip;
80
81 architecture structural of chip is
82
83 component corona
84 port ( eint_0_from_pad : in bit
85 ; eint_1_from_pad : in bit
86 ; eint_2_from_pad : in bit
87 ; i2c_sda_i_from_pad : in bit
88 ; jtag_tck_from_pad : in bit
89 ; jtag_tdi_from_pad : in bit
90 ; jtag_tms_from_pad : in bit
91 ; spimaster_miso_from_pad : in bit
92 ; sys_clk_from_pad : in bit
93 ; sys_rst_from_pad : in bit
94 ; uart_rx_from_pad : in bit
95 ; uart_tx_from_pad : in bit
96 ; gpio_i_from_pad : in bit_vector(15 downto 0)
97 ; sdram_dq_i_from_pad : in bit_vector(15 downto 0)
98 ; nc_from_pad : in bit_vector(39 downto 0)
99 ; eint_0_enable_to_pad : out bit
100 ; eint_1_enable_to_pad : out bit
101 ; eint_2_enable_to_pad : out bit
102 ; i2c_scl_enable_to_pad : out bit
103 ; i2c_scl_to_pad : out bit
104 ; i2c_sda_o_to_pad : out bit
105 ; i2c_sda_oe_to_pad : out bit
106 ; jtag_tck_enable_to_pad : out bit
107 ; jtag_tdi_enable_to_pad : out bit
108 ; jtag_tdo_enable_to_pad : out bit
109 ; jtag_tdo_to_pad : out bit
110 ; jtag_tms_enable_to_pad : out bit
111 ; nc_0_enable_to_pad : out bit
112 ; nc_10_enable_to_pad : out bit
113 ; nc_11_enable_to_pad : out bit
114 ; nc_12_enable_to_pad : out bit
115 ; nc_13_enable_to_pad : out bit
116 ; nc_14_enable_to_pad : out bit
117 ; nc_15_enable_to_pad : out bit
118 ; nc_16_enable_to_pad : out bit
119 ; nc_17_enable_to_pad : out bit
120 ; nc_18_enable_to_pad : out bit
121 ; nc_19_enable_to_pad : out bit
122 ; nc_1_enable_to_pad : out bit
123 ; nc_20_enable_to_pad : out bit
124 ; nc_21_enable_to_pad : out bit
125 ; nc_22_enable_to_pad : out bit
126 ; nc_23_enable_to_pad : out bit
127 ; nc_24_enable_to_pad : out bit
128 ; nc_25_enable_to_pad : out bit
129 ; nc_26_enable_to_pad : out bit
130 ; nc_27_enable_to_pad : out bit
131 ; nc_28_enable_to_pad : out bit
132 ; nc_29_enable_to_pad : out bit
133 ; nc_2_enable_to_pad : out bit
134 ; nc_30_enable_to_pad : out bit
135 ; nc_31_enable_to_pad : out bit
136 ; nc_32_enable_to_pad : out bit
137 ; nc_33_enable_to_pad : out bit
138 ; nc_34_enable_to_pad : out bit
139 ; nc_35_enable_to_pad : out bit
140 ; nc_36_enable_to_pad : out bit
141 ; nc_37_enable_to_pad : out bit
142 ; nc_38_enable_to_pad : out bit
143 ; nc_39_enable_to_pad : out bit
144 ; nc_3_enable_to_pad : out bit
145 ; nc_4_enable_to_pad : out bit
146 ; nc_5_enable_to_pad : out bit
147 ; nc_6_enable_to_pad : out bit
148 ; nc_7_enable_to_pad : out bit
149 ; nc_8_enable_to_pad : out bit
150 ; nc_9_enable_to_pad : out bit
151 ; sdram_a_0_enable_to_pad : out bit
152 ; sdram_a_10_enable_to_pad : out bit
153 ; sdram_a_11_enable_to_pad : out bit
154 ; sdram_a_12_enable_to_pad : out bit
155 ; sdram_a_1_enable_to_pad : out bit
156 ; sdram_a_2_enable_to_pad : out bit
157 ; sdram_a_3_enable_to_pad : out bit
158 ; sdram_a_4_enable_to_pad : out bit
159 ; sdram_a_5_enable_to_pad : out bit
160 ; sdram_a_6_enable_to_pad : out bit
161 ; sdram_a_7_enable_to_pad : out bit
162 ; sdram_a_8_enable_to_pad : out bit
163 ; sdram_a_9_enable_to_pad : out bit
164 ; sdram_ba_0_enable_to_pad : out bit
165 ; sdram_ba_1_enable_to_pad : out bit
166 ; sdram_cas_n_enable_to_pad : out bit
167 ; sdram_cas_n_to_pad : out bit
168 ; sdram_cke_enable_to_pad : out bit
169 ; sdram_cke_to_pad : out bit
170 ; sdram_clock_enable_to_pad : out bit
171 ; sdram_clock_to_pad : out bit
172 ; sdram_cs_n_enable_to_pad : out bit
173 ; sdram_cs_n_to_pad : out bit
174 ; sdram_dm_0_enable_to_pad : out bit
175 ; sdram_dm_1_enable_to_pad : out bit
176 ; sdram_ras_n_enable_to_pad : out bit
177 ; sdram_ras_n_to_pad : out bit
178 ; sdram_we_n_enable_to_pad : out bit
179 ; sdram_we_n_to_pad : out bit
180 ; spimaster_clk_enable_to_pad : out bit
181 ; spimaster_clk_to_pad : out bit
182 ; spimaster_cs_n_enable_to_pad : out bit
183 ; spimaster_cs_n_to_pad : out bit
184 ; spimaster_miso_enable_to_pad : out bit
185 ; spimaster_mosi_enable_to_pad : out bit
186 ; spimaster_mosi_to_pad : out bit
187 ; sys_clk_enable_to_pad : out bit
188 ; sys_rst_enable_to_pad : out bit
189 ; uart_rx_enable_to_pad : out bit
190 ; uart_tx_enable_to_pad : out bit
191 ; sdram_ba_to_pad : out bit_vector(1 downto 0)
192 ; sdram_dm_to_pad : out bit_vector(1 downto 0)
193 ; sdram_a_to_pad : out bit_vector(12 downto 0)
194 ; gpio_o_to_pad : out bit_vector(15 downto 0)
195 ; gpio_oe_to_pad : out bit_vector(15 downto 0)
196 ; sdram_dq_o_to_pad : out bit_vector(15 downto 0)
197 ; sdram_dq_oe_to_pad : out bit_vector(15 downto 0)
198 ; vdd : in bit
199 ; vss : in bit
200 );
201 end component;
202
203 component cmpt_iovss
204 port ( iovdd : in bit
205 ; iovss : in bit
206 ; vdd : in bit
207 ; vss : in bit
208 );
209 end component;
210
211 component cmpt_iovdd
212 port ( iovdd : in bit
213 ; iovss : in bit
214 ; vdd : in bit
215 ; vss : in bit
216 );
217 end component;
218
219 component cmpt_vss
220 port ( iovdd : in bit
221 ; iovss : in bit
222 ; vdd : in bit
223 ; vss : in bit
224 );
225 end component;
226
227 component cmpt_vdd
228 port ( iovdd : in bit
229 ; iovss : in bit
230 ; vdd : in bit
231 ; vss : in bit
232 );
233 end component;
234
235 component cmpt_gpio
236 port ( i : in bit
237 ; oe : in bit
238 ; o : out bit
239 ; pad : inout STD_LOGIC
240 ; iovdd : in bit
241 ; iovss : in bit
242 ; vdd : in bit
243 ; vss : in bit
244 );
245 end component;
246
247 signal chip_dummy_0 : bit;
248 signal chip_dummy_1 : bit;
249 signal chip_dummy_10 : bit;
250 signal chip_dummy_11 : bit;
251 signal chip_dummy_12 : bit;
252 signal chip_dummy_13 : bit;
253 signal chip_dummy_14 : bit;
254 signal chip_dummy_15 : bit;
255 signal chip_dummy_16 : bit;
256 signal chip_dummy_17 : bit;
257 signal chip_dummy_18 : bit;
258 signal chip_dummy_19 : bit;
259 signal chip_dummy_2 : bit;
260 signal chip_dummy_20 : bit;
261 signal chip_dummy_21 : bit;
262 signal chip_dummy_22 : bit;
263 signal chip_dummy_23 : bit;
264 signal chip_dummy_24 : bit;
265 signal chip_dummy_25 : bit;
266 signal chip_dummy_26 : bit;
267 signal chip_dummy_27 : bit;
268 signal chip_dummy_28 : bit;
269 signal chip_dummy_29 : bit;
270 signal chip_dummy_3 : bit;
271 signal chip_dummy_30 : bit;
272 signal chip_dummy_31 : bit;
273 signal chip_dummy_32 : bit;
274 signal chip_dummy_33 : bit;
275 signal chip_dummy_34 : bit;
276 signal chip_dummy_35 : bit;
277 signal chip_dummy_36 : bit;
278 signal chip_dummy_37 : bit;
279 signal chip_dummy_38 : bit;
280 signal chip_dummy_39 : bit;
281 signal chip_dummy_4 : bit;
282 signal chip_dummy_40 : bit;
283 signal chip_dummy_41 : bit;
284 signal chip_dummy_42 : bit;
285 signal chip_dummy_43 : bit;
286 signal chip_dummy_44 : bit;
287 signal chip_dummy_45 : bit;
288 signal chip_dummy_46 : bit;
289 signal chip_dummy_47 : bit;
290 signal chip_dummy_48 : bit;
291 signal chip_dummy_49 : bit;
292 signal chip_dummy_5 : bit;
293 signal chip_dummy_50 : bit;
294 signal chip_dummy_51 : bit;
295 signal chip_dummy_52 : bit;
296 signal chip_dummy_53 : bit;
297 signal chip_dummy_54 : bit;
298 signal chip_dummy_55 : bit;
299 signal chip_dummy_56 : bit;
300 signal chip_dummy_57 : bit;
301 signal chip_dummy_58 : bit;
302 signal chip_dummy_59 : bit;
303 signal chip_dummy_6 : bit;
304 signal chip_dummy_60 : bit;
305 signal chip_dummy_61 : bit;
306 signal chip_dummy_62 : bit;
307 signal chip_dummy_63 : bit;
308 signal chip_dummy_64 : bit;
309 signal chip_dummy_65 : bit;
310 signal chip_dummy_66 : bit;
311 signal chip_dummy_67 : bit;
312 signal chip_dummy_68 : bit;
313 signal chip_dummy_69 : bit;
314 signal chip_dummy_7 : bit;
315 signal chip_dummy_70 : bit;
316 signal chip_dummy_71 : bit;
317 signal chip_dummy_72 : bit;
318 signal chip_dummy_73 : bit;
319 signal chip_dummy_74 : bit;
320 signal chip_dummy_75 : bit;
321 signal chip_dummy_76 : bit;
322 signal chip_dummy_77 : bit;
323 signal chip_dummy_78 : bit;
324 signal chip_dummy_8 : bit;
325 signal chip_dummy_9 : bit;
326 signal eint_0_enable_to_pad : bit;
327 signal eint_0_from_pad : bit;
328 signal eint_1_enable_to_pad : bit;
329 signal eint_1_from_pad : bit;
330 signal eint_2_enable_to_pad : bit;
331 signal eint_2_from_pad : bit;
332 signal i2c_scl_enable_to_pad : bit;
333 signal i2c_scl_to_pad : bit;
334 signal i2c_sda_i_from_pad : bit;
335 signal i2c_sda_o_to_pad : bit;
336 signal i2c_sda_oe_to_pad : bit;
337 signal jtag_tck_enable_to_pad : bit;
338 signal jtag_tck_from_pad : bit;
339 signal jtag_tdi_enable_to_pad : bit;
340 signal jtag_tdi_from_pad : bit;
341 signal jtag_tdo_enable_to_pad : bit;
342 signal jtag_tdo_to_pad : bit;
343 signal jtag_tms_enable_to_pad : bit;
344 signal jtag_tms_from_pad : bit;
345 signal nc_0_enable_to_pad : bit;
346 signal nc_10_enable_to_pad : bit;
347 signal nc_11_enable_to_pad : bit;
348 signal nc_12_enable_to_pad : bit;
349 signal nc_13_enable_to_pad : bit;
350 signal nc_14_enable_to_pad : bit;
351 signal nc_15_enable_to_pad : bit;
352 signal nc_16_enable_to_pad : bit;
353 signal nc_17_enable_to_pad : bit;
354 signal nc_18_enable_to_pad : bit;
355 signal nc_19_enable_to_pad : bit;
356 signal nc_1_enable_to_pad : bit;
357 signal nc_20_enable_to_pad : bit;
358 signal nc_21_enable_to_pad : bit;
359 signal nc_22_enable_to_pad : bit;
360 signal nc_23_enable_to_pad : bit;
361 signal nc_24_enable_to_pad : bit;
362 signal nc_25_enable_to_pad : bit;
363 signal nc_26_enable_to_pad : bit;
364 signal nc_27_enable_to_pad : bit;
365 signal nc_28_enable_to_pad : bit;
366 signal nc_29_enable_to_pad : bit;
367 signal nc_2_enable_to_pad : bit;
368 signal nc_30_enable_to_pad : bit;
369 signal nc_31_enable_to_pad : bit;
370 signal nc_32_enable_to_pad : bit;
371 signal nc_33_enable_to_pad : bit;
372 signal nc_34_enable_to_pad : bit;
373 signal nc_35_enable_to_pad : bit;
374 signal nc_36_enable_to_pad : bit;
375 signal nc_37_enable_to_pad : bit;
376 signal nc_38_enable_to_pad : bit;
377 signal nc_39_enable_to_pad : bit;
378 signal nc_3_enable_to_pad : bit;
379 signal nc_4_enable_to_pad : bit;
380 signal nc_5_enable_to_pad : bit;
381 signal nc_6_enable_to_pad : bit;
382 signal nc_7_enable_to_pad : bit;
383 signal nc_8_enable_to_pad : bit;
384 signal nc_9_enable_to_pad : bit;
385 signal sdram_a_0_enable_to_pad : bit;
386 signal sdram_a_10_enable_to_pad : bit;
387 signal sdram_a_11_enable_to_pad : bit;
388 signal sdram_a_12_enable_to_pad : bit;
389 signal sdram_a_1_enable_to_pad : bit;
390 signal sdram_a_2_enable_to_pad : bit;
391 signal sdram_a_3_enable_to_pad : bit;
392 signal sdram_a_4_enable_to_pad : bit;
393 signal sdram_a_5_enable_to_pad : bit;
394 signal sdram_a_6_enable_to_pad : bit;
395 signal sdram_a_7_enable_to_pad : bit;
396 signal sdram_a_8_enable_to_pad : bit;
397 signal sdram_a_9_enable_to_pad : bit;
398 signal sdram_ba_0_enable_to_pad : bit;
399 signal sdram_ba_1_enable_to_pad : bit;
400 signal sdram_cas_n_enable_to_pad : bit;
401 signal sdram_cas_n_to_pad : bit;
402 signal sdram_cke_enable_to_pad : bit;
403 signal sdram_cke_to_pad : bit;
404 signal sdram_clock_enable_to_pad : bit;
405 signal sdram_clock_to_pad : bit;
406 signal sdram_cs_n_enable_to_pad : bit;
407 signal sdram_cs_n_to_pad : bit;
408 signal sdram_dm_0_enable_to_pad : bit;
409 signal sdram_dm_1_enable_to_pad : bit;
410 signal sdram_ras_n_enable_to_pad : bit;
411 signal sdram_ras_n_to_pad : bit;
412 signal sdram_we_n_enable_to_pad : bit;
413 signal sdram_we_n_to_pad : bit;
414 signal spimaster_clk_enable_to_pad : bit;
415 signal spimaster_clk_to_pad : bit;
416 signal spimaster_cs_n_enable_to_pad : bit;
417 signal spimaster_cs_n_to_pad : bit;
418 signal spimaster_miso_enable_to_pad : bit;
419 signal spimaster_miso_from_pad : bit;
420 signal spimaster_mosi_enable_to_pad : bit;
421 signal spimaster_mosi_to_pad : bit;
422 signal sys_clk_enable_to_pad : bit;
423 signal sys_clk_from_pad : bit;
424 signal sys_rst_enable_to_pad : bit;
425 signal sys_rst_from_pad : bit;
426 signal uart_rx_enable_to_pad : bit;
427 signal uart_rx_from_pad : bit;
428 signal uart_tx_enable_to_pad : bit;
429 signal uart_tx_from_pad : bit;
430 signal sdram_ba_to_pad : bit_vector(1 downto 0);
431 signal sdram_dm_to_pad : bit_vector(1 downto 0);
432 signal sdram_a_to_pad : bit_vector(12 downto 0);
433 signal gpio_i_from_pad : bit_vector(15 downto 0);
434 signal gpio_o_to_pad : bit_vector(15 downto 0);
435 signal gpio_oe_to_pad : bit_vector(15 downto 0);
436 signal sdram_dq_i_from_pad : bit_vector(15 downto 0);
437 signal sdram_dq_o_to_pad : bit_vector(15 downto 0);
438 signal sdram_dq_oe_to_pad : bit_vector(15 downto 0);
439 signal nc_from_pad : bit_vector(39 downto 0);
440
441
442 begin
443
444 p_sys_rst : cmpt_gpio
445 port map ( i => sys_rst_from_pad
446 , oe => sys_rst_enable_to_pad
447 , o => chip_dummy_73
448 , pad => sys_rst
449 , iovdd => iovdd
450 , iovss => iovss
451 , vdd => vdd
452 , vss => vss
453 );
454
455 p_gpio_15 : cmpt_gpio
456 port map ( i => gpio_o_to_pad(15)
457 , oe => gpio_oe_to_pad(15)
458 , o => gpio_i_from_pad(15)
459 , pad => gpio_15
460 , iovdd => iovdd
461 , iovss => iovss
462 , vdd => vdd
463 , vss => vss
464 );
465
466 p_gpio_14 : cmpt_gpio
467 port map ( i => gpio_o_to_pad(14)
468 , oe => gpio_oe_to_pad(14)
469 , o => gpio_i_from_pad(14)
470 , pad => gpio_14
471 , iovdd => iovdd
472 , iovss => iovss
473 , vdd => vdd
474 , vss => vss
475 );
476
477 p_gpio_13 : cmpt_gpio
478 port map ( i => gpio_o_to_pad(13)
479 , oe => gpio_oe_to_pad(13)
480 , o => gpio_i_from_pad(13)
481 , pad => gpio_13
482 , iovdd => iovdd
483 , iovss => iovss
484 , vdd => vdd
485 , vss => vss
486 );
487
488 p_gpio_12 : cmpt_gpio
489 port map ( i => gpio_o_to_pad(12)
490 , oe => gpio_oe_to_pad(12)
491 , o => gpio_i_from_pad(12)
492 , pad => gpio_12
493 , iovdd => iovdd
494 , iovss => iovss
495 , vdd => vdd
496 , vss => vss
497 );
498
499 p_gpio_11 : cmpt_gpio
500 port map ( i => gpio_o_to_pad(11)
501 , oe => gpio_oe_to_pad(11)
502 , o => gpio_i_from_pad(11)
503 , pad => gpio_11
504 , iovdd => iovdd
505 , iovss => iovss
506 , vdd => vdd
507 , vss => vss
508 );
509
510 p_gpio_10 : cmpt_gpio
511 port map ( i => gpio_o_to_pad(10)
512 , oe => gpio_oe_to_pad(10)
513 , o => gpio_i_from_pad(10)
514 , pad => gpio_10
515 , iovdd => iovdd
516 , iovss => iovss
517 , vdd => vdd
518 , vss => vss
519 );
520
521 p_sdram_dm_1 : cmpt_gpio
522 port map ( i => chip_dummy_3
523 , oe => sdram_dm_1_enable_to_pad
524 , o => sdram_dm_to_pad(1)
525 , pad => sdram_dm(1)
526 , iovdd => iovdd
527 , iovss => iovss
528 , vdd => vdd
529 , vss => vss
530 );
531
532 p_sdram_dm_0 : cmpt_gpio
533 port map ( i => chip_dummy_40
534 , oe => sdram_dm_0_enable_to_pad
535 , o => sdram_dm_to_pad(0)
536 , pad => sdram_dm(0)
537 , iovdd => iovdd
538 , iovss => iovss
539 , vdd => vdd
540 , vss => vss
541 );
542
543 nc_39 : cmpt_gpio
544 port map ( i => nc_from_pad(39)
545 , oe => nc_39_enable_to_pad
546 , o => chip_dummy_78
547 , pad => nc(39)
548 , iovdd => iovdd
549 , iovss => iovss
550 , vdd => vdd
551 , vss => vss
552 );
553
554 nc_38 : cmpt_gpio
555 port map ( i => nc_from_pad(38)
556 , oe => nc_38_enable_to_pad
557 , o => chip_dummy_77
558 , pad => nc(38)
559 , iovdd => iovdd
560 , iovss => iovss
561 , vdd => vdd
562 , vss => vss
563 );
564
565 nc_37 : cmpt_gpio
566 port map ( i => nc_from_pad(37)
567 , oe => nc_37_enable_to_pad
568 , o => chip_dummy_76
569 , pad => nc(37)
570 , iovdd => iovdd
571 , iovss => iovss
572 , vdd => vdd
573 , vss => vss
574 );
575
576 nc_36 : cmpt_gpio
577 port map ( i => nc_from_pad(36)
578 , oe => nc_36_enable_to_pad
579 , o => chip_dummy_75
580 , pad => nc(36)
581 , iovdd => iovdd
582 , iovss => iovss
583 , vdd => vdd
584 , vss => vss
585 );
586
587 nc_35 : cmpt_gpio
588 port map ( i => nc_from_pad(35)
589 , oe => nc_35_enable_to_pad
590 , o => chip_dummy_74
591 , pad => nc(35)
592 , iovdd => iovdd
593 , iovss => iovss
594 , vdd => vdd
595 , vss => vss
596 );
597
598 nc_34 : cmpt_gpio
599 port map ( i => nc_from_pad(34)
600 , oe => nc_34_enable_to_pad
601 , o => chip_dummy_69
602 , pad => nc(34)
603 , iovdd => iovdd
604 , iovss => iovss
605 , vdd => vdd
606 , vss => vss
607 );
608
609 nc_33 : cmpt_gpio
610 port map ( i => nc_from_pad(33)
611 , oe => nc_33_enable_to_pad
612 , o => chip_dummy_64
613 , pad => nc(33)
614 , iovdd => iovdd
615 , iovss => iovss
616 , vdd => vdd
617 , vss => vss
618 );
619
620 nc_32 : cmpt_gpio
621 port map ( i => nc_from_pad(32)
622 , oe => nc_32_enable_to_pad
623 , o => chip_dummy_63
624 , pad => nc(32)
625 , iovdd => iovdd
626 , iovss => iovss
627 , vdd => vdd
628 , vss => vss
629 );
630
631 nc_31 : cmpt_gpio
632 port map ( i => nc_from_pad(31)
633 , oe => nc_31_enable_to_pad
634 , o => chip_dummy_62
635 , pad => nc(31)
636 , iovdd => iovdd
637 , iovss => iovss
638 , vdd => vdd
639 , vss => vss
640 );
641
642 nc_30 : cmpt_gpio
643 port map ( i => nc_from_pad(30)
644 , oe => nc_30_enable_to_pad
645 , o => chip_dummy_61
646 , pad => nc(30)
647 , iovdd => iovdd
648 , iovss => iovss
649 , vdd => vdd
650 , vss => vss
651 );
652
653 p_sdram_dq_7 : cmpt_gpio
654 port map ( i => sdram_dq_o_to_pad(7)
655 , oe => sdram_dq_oe_to_pad(7)
656 , o => sdram_dq_i_from_pad(7)
657 , pad => sdram_dq_7
658 , iovdd => iovdd
659 , iovss => iovss
660 , vdd => vdd
661 , vss => vss
662 );
663
664 p_sdram_dq_9 : cmpt_gpio
665 port map ( i => sdram_dq_o_to_pad(9)
666 , oe => sdram_dq_oe_to_pad(9)
667 , o => sdram_dq_i_from_pad(9)
668 , pad => sdram_dq_9
669 , iovdd => iovdd
670 , iovss => iovss
671 , vdd => vdd
672 , vss => vss
673 );
674
675 p_sdram_dq_8 : cmpt_gpio
676 port map ( i => sdram_dq_o_to_pad(8)
677 , oe => sdram_dq_oe_to_pad(8)
678 , o => sdram_dq_i_from_pad(8)
679 , pad => sdram_dq_8
680 , iovdd => iovdd
681 , iovss => iovss
682 , vdd => vdd
683 , vss => vss
684 );
685
686 p_sdram_dq_0 : cmpt_gpio
687 port map ( i => sdram_dq_o_to_pad(0)
688 , oe => sdram_dq_oe_to_pad(0)
689 , o => sdram_dq_i_from_pad(0)
690 , pad => sdram_dq_0
691 , iovdd => iovdd
692 , iovss => iovss
693 , vdd => vdd
694 , vss => vss
695 );
696
697 p_sdram_dq_1 : cmpt_gpio
698 port map ( i => sdram_dq_o_to_pad(1)
699 , oe => sdram_dq_oe_to_pad(1)
700 , o => sdram_dq_i_from_pad(1)
701 , pad => sdram_dq_1
702 , iovdd => iovdd
703 , iovss => iovss
704 , vdd => vdd
705 , vss => vss
706 );
707
708 p_sdram_dq_2 : cmpt_gpio
709 port map ( i => sdram_dq_o_to_pad(2)
710 , oe => sdram_dq_oe_to_pad(2)
711 , o => sdram_dq_i_from_pad(2)
712 , pad => sdram_dq_2
713 , iovdd => iovdd
714 , iovss => iovss
715 , vdd => vdd
716 , vss => vss
717 );
718
719 p_sdram_dq_3 : cmpt_gpio
720 port map ( i => sdram_dq_o_to_pad(3)
721 , oe => sdram_dq_oe_to_pad(3)
722 , o => sdram_dq_i_from_pad(3)
723 , pad => sdram_dq_3
724 , iovdd => iovdd
725 , iovss => iovss
726 , vdd => vdd
727 , vss => vss
728 );
729
730 p_sdram_dq_4 : cmpt_gpio
731 port map ( i => sdram_dq_o_to_pad(4)
732 , oe => sdram_dq_oe_to_pad(4)
733 , o => sdram_dq_i_from_pad(4)
734 , pad => sdram_dq_4
735 , iovdd => iovdd
736 , iovss => iovss
737 , vdd => vdd
738 , vss => vss
739 );
740
741 p_sdram_dq_5 : cmpt_gpio
742 port map ( i => sdram_dq_o_to_pad(5)
743 , oe => sdram_dq_oe_to_pad(5)
744 , o => sdram_dq_i_from_pad(5)
745 , pad => sdram_dq_5
746 , iovdd => iovdd
747 , iovss => iovss
748 , vdd => vdd
749 , vss => vss
750 );
751
752 p_sdram_dq_6 : cmpt_gpio
753 port map ( i => sdram_dq_o_to_pad(6)
754 , oe => sdram_dq_oe_to_pad(6)
755 , o => sdram_dq_i_from_pad(6)
756 , pad => sdram_dq_6
757 , iovdd => iovdd
758 , iovss => iovss
759 , vdd => vdd
760 , vss => vss
761 );
762
763 p_uart_rx : cmpt_gpio
764 port map ( i => uart_rx_from_pad
765 , oe => uart_rx_enable_to_pad
766 , o => chip_dummy_71
767 , pad => uart_rx
768 , iovdd => iovdd
769 , iovss => iovss
770 , vdd => vdd
771 , vss => vss
772 );
773
774 p_spimaster_mosi : cmpt_gpio
775 port map ( i => chip_dummy_67
776 , oe => spimaster_mosi_enable_to_pad
777 , o => spimaster_mosi_to_pad
778 , pad => spimaster_mosi
779 , iovdd => iovdd
780 , iovss => iovss
781 , vdd => vdd
782 , vss => vss
783 );
784
785 p_sdram_ba_1 : cmpt_gpio
786 port map ( i => chip_dummy_52
787 , oe => sdram_ba_1_enable_to_pad
788 , o => sdram_ba_to_pad(1)
789 , pad => sdram_ba(1)
790 , iovdd => iovdd
791 , iovss => iovss
792 , vdd => vdd
793 , vss => vss
794 );
795
796 p_sdram_ba_0 : cmpt_gpio
797 port map ( i => chip_dummy_51
798 , oe => sdram_ba_0_enable_to_pad
799 , o => sdram_ba_to_pad(0)
800 , pad => sdram_ba(0)
801 , iovdd => iovdd
802 , iovss => iovss
803 , vdd => vdd
804 , vss => vss
805 );
806
807 p_i2c_scl : cmpt_gpio
808 port map ( i => chip_dummy_60
809 , oe => i2c_scl_enable_to_pad
810 , o => i2c_scl_to_pad
811 , pad => i2c_scl
812 , iovdd => iovdd
813 , iovss => iovss
814 , vdd => vdd
815 , vss => vss
816 );
817
818 p_vdd_4 : cmpt_vdd
819 port map ( iovdd => iovdd
820 , iovss => iovss
821 , vdd => vdd
822 , vss => vss
823 );
824
825 p_vdd_1 : cmpt_vdd
826 port map ( iovdd => iovdd
827 , iovss => iovss
828 , vdd => vdd
829 , vss => vss
830 );
831
832 p_vdd_0 : cmpt_vdd
833 port map ( iovdd => iovdd
834 , iovss => iovss
835 , vdd => vdd
836 , vss => vss
837 );
838
839 p_vdd_2 : cmpt_vdd
840 port map ( iovdd => iovdd
841 , iovss => iovss
842 , vdd => vdd
843 , vss => vss
844 );
845
846 p_vdd_3 : cmpt_vdd
847 port map ( iovdd => iovdd
848 , iovss => iovss
849 , vdd => vdd
850 , vss => vss
851 );
852
853 p_sdram_cs_n : cmpt_gpio
854 port map ( i => chip_dummy_58
855 , oe => sdram_cs_n_enable_to_pad
856 , o => sdram_cs_n_to_pad
857 , pad => sdram_cs_n
858 , iovdd => iovdd
859 , iovss => iovss
860 , vdd => vdd
861 , vss => vss
862 );
863
864 p_iovss_0 : cmpt_iovss
865 port map ( iovdd => iovdd
866 , iovss => iovss
867 , vdd => vdd
868 , vss => vss
869 );
870
871 p_iovss_2 : cmpt_iovss
872 port map ( iovdd => iovdd
873 , iovss => iovss
874 , vdd => vdd
875 , vss => vss
876 );
877
878 p_iovss_1 : cmpt_iovss
879 port map ( iovdd => iovdd
880 , iovss => iovss
881 , vdd => vdd
882 , vss => vss
883 );
884
885 p_sys_clk : cmpt_gpio
886 port map ( i => sys_clk_from_pad
887 , oe => sys_clk_enable_to_pad
888 , o => chip_dummy_72
889 , pad => sys_clk
890 , iovdd => iovdd
891 , iovss => iovss
892 , vdd => vdd
893 , vss => vss
894 );
895
896 p_i2c_sda : cmpt_gpio
897 port map ( i => i2c_sda_o_to_pad
898 , oe => i2c_sda_oe_to_pad
899 , o => i2c_sda_i_from_pad
900 , pad => i2c_sda
901 , iovdd => iovdd
902 , iovss => iovss
903 , vdd => vdd
904 , vss => vss
905 );
906
907 p_sdram_a_10 : cmpt_gpio
908 port map ( i => chip_dummy_0
909 , oe => sdram_a_10_enable_to_pad
910 , o => sdram_a_to_pad(10)
911 , pad => sdram_a(10)
912 , iovdd => iovdd
913 , iovss => iovss
914 , vdd => vdd
915 , vss => vss
916 );
917
918 p_sdram_a_11 : cmpt_gpio
919 port map ( i => chip_dummy_1
920 , oe => sdram_a_11_enable_to_pad
921 , o => sdram_a_to_pad(11)
922 , pad => sdram_a(11)
923 , iovdd => iovdd
924 , iovss => iovss
925 , vdd => vdd
926 , vss => vss
927 );
928
929 p_sdram_a_12 : cmpt_gpio
930 port map ( i => chip_dummy_2
931 , oe => sdram_a_12_enable_to_pad
932 , o => sdram_a_to_pad(12)
933 , pad => sdram_a(12)
934 , iovdd => iovdd
935 , iovss => iovss
936 , vdd => vdd
937 , vss => vss
938 );
939
940 p_uart_tx : cmpt_gpio
941 port map ( i => uart_tx_from_pad
942 , oe => uart_tx_enable_to_pad
943 , o => chip_dummy_70
944 , pad => uart_tx
945 , iovdd => iovdd
946 , iovss => iovss
947 , vdd => vdd
948 , vss => vss
949 );
950
951 nc_0 : cmpt_gpio
952 port map ( i => nc_from_pad(0)
953 , oe => nc_0_enable_to_pad
954 , o => chip_dummy_4
955 , pad => nc(0)
956 , iovdd => iovdd
957 , iovss => iovss
958 , vdd => vdd
959 , vss => vss
960 );
961
962 p_jtag_tck : cmpt_gpio
963 port map ( i => jtag_tck_from_pad
964 , oe => jtag_tck_enable_to_pad
965 , o => chip_dummy_8
966 , pad => jtag_tck
967 , iovdd => iovdd
968 , iovss => iovss
969 , vdd => vdd
970 , vss => vss
971 );
972
973 nc_1 : cmpt_gpio
974 port map ( i => nc_from_pad(1)
975 , oe => nc_1_enable_to_pad
976 , o => chip_dummy_9
977 , pad => nc(1)
978 , iovdd => iovdd
979 , iovss => iovss
980 , vdd => vdd
981 , vss => vss
982 );
983
984 nc_2 : cmpt_gpio
985 port map ( i => nc_from_pad(2)
986 , oe => nc_2_enable_to_pad
987 , o => chip_dummy_10
988 , pad => nc(2)
989 , iovdd => iovdd
990 , iovss => iovss
991 , vdd => vdd
992 , vss => vss
993 );
994
995 nc_3 : cmpt_gpio
996 port map ( i => nc_from_pad(3)
997 , oe => nc_3_enable_to_pad
998 , o => chip_dummy_11
999 , pad => nc(3)
1000 , iovdd => iovdd
1001 , iovss => iovss
1002 , vdd => vdd
1003 , vss => vss
1004 );
1005
1006 nc_4 : cmpt_gpio
1007 port map ( i => nc_from_pad(4)
1008 , oe => nc_4_enable_to_pad
1009 , o => chip_dummy_12
1010 , pad => nc(4)
1011 , iovdd => iovdd
1012 , iovss => iovss
1013 , vdd => vdd
1014 , vss => vss
1015 );
1016
1017 nc_5 : cmpt_gpio
1018 port map ( i => nc_from_pad(5)
1019 , oe => nc_5_enable_to_pad
1020 , o => chip_dummy_13
1021 , pad => nc(5)
1022 , iovdd => iovdd
1023 , iovss => iovss
1024 , vdd => vdd
1025 , vss => vss
1026 );
1027
1028 nc_6 : cmpt_gpio
1029 port map ( i => nc_from_pad(6)
1030 , oe => nc_6_enable_to_pad
1031 , o => chip_dummy_17
1032 , pad => nc(6)
1033 , iovdd => iovdd
1034 , iovss => iovss
1035 , vdd => vdd
1036 , vss => vss
1037 );
1038
1039 nc_7 : cmpt_gpio
1040 port map ( i => nc_from_pad(7)
1041 , oe => nc_7_enable_to_pad
1042 , o => chip_dummy_18
1043 , pad => nc(7)
1044 , iovdd => iovdd
1045 , iovss => iovss
1046 , vdd => vdd
1047 , vss => vss
1048 );
1049
1050 nc_8 : cmpt_gpio
1051 port map ( i => nc_from_pad(8)
1052 , oe => nc_8_enable_to_pad
1053 , o => chip_dummy_19
1054 , pad => nc(8)
1055 , iovdd => iovdd
1056 , iovss => iovss
1057 , vdd => vdd
1058 , vss => vss
1059 );
1060
1061 nc_9 : cmpt_gpio
1062 port map ( i => nc_from_pad(9)
1063 , oe => nc_9_enable_to_pad
1064 , o => chip_dummy_20
1065 , pad => nc(9)
1066 , iovdd => iovdd
1067 , iovss => iovss
1068 , vdd => vdd
1069 , vss => vss
1070 );
1071
1072 p_sdram_ras_n : cmpt_gpio
1073 port map ( i => chip_dummy_55
1074 , oe => sdram_ras_n_enable_to_pad
1075 , o => sdram_ras_n_to_pad
1076 , pad => sdram_ras_n
1077 , iovdd => iovdd
1078 , iovss => iovss
1079 , vdd => vdd
1080 , vss => vss
1081 );
1082
1083 p_jtag_tdo : cmpt_gpio
1084 port map ( i => chip_dummy_7
1085 , oe => jtag_tdo_enable_to_pad
1086 , o => jtag_tdo_to_pad
1087 , pad => jtag_tdo
1088 , iovdd => iovdd
1089 , iovss => iovss
1090 , vdd => vdd
1091 , vss => vss
1092 );
1093
1094 p_jtag_tdi : cmpt_gpio
1095 port map ( i => jtag_tdi_from_pad
1096 , oe => jtag_tdi_enable_to_pad
1097 , o => chip_dummy_6
1098 , pad => jtag_tdi
1099 , iovdd => iovdd
1100 , iovss => iovss
1101 , vdd => vdd
1102 , vss => vss
1103 );
1104
1105 p_vss_4 : cmpt_vss
1106 port map ( iovdd => iovdd
1107 , iovss => iovss
1108 , vdd => vdd
1109 , vss => vss
1110 );
1111
1112 p_vss_1 : cmpt_vss
1113 port map ( iovdd => iovdd
1114 , iovss => iovss
1115 , vdd => vdd
1116 , vss => vss
1117 );
1118
1119 p_vss_0 : cmpt_vss
1120 port map ( iovdd => iovdd
1121 , iovss => iovss
1122 , vdd => vdd
1123 , vss => vss
1124 );
1125
1126 p_vss_2 : cmpt_vss
1127 port map ( iovdd => iovdd
1128 , iovss => iovss
1129 , vdd => vdd
1130 , vss => vss
1131 );
1132
1133 p_vss_3 : cmpt_vss
1134 port map ( iovdd => iovdd
1135 , iovss => iovss
1136 , vdd => vdd
1137 , vss => vss
1138 );
1139
1140 p_spimaster_miso : cmpt_gpio
1141 port map ( i => spimaster_miso_from_pad
1142 , oe => spimaster_miso_enable_to_pad
1143 , o => chip_dummy_68
1144 , pad => spimaster_miso
1145 , iovdd => iovdd
1146 , iovss => iovss
1147 , vdd => vdd
1148 , vss => vss
1149 );
1150
1151 p_spimaster_cs_n : cmpt_gpio
1152 port map ( i => chip_dummy_66
1153 , oe => spimaster_cs_n_enable_to_pad
1154 , o => spimaster_cs_n_to_pad
1155 , pad => spimaster_cs_n
1156 , iovdd => iovdd
1157 , iovss => iovss
1158 , vdd => vdd
1159 , vss => vss
1160 );
1161
1162 p_spimaster_clk : cmpt_gpio
1163 port map ( i => chip_dummy_65
1164 , oe => spimaster_clk_enable_to_pad
1165 , o => spimaster_clk_to_pad
1166 , pad => spimaster_clk
1167 , iovdd => iovdd
1168 , iovss => iovss
1169 , vdd => vdd
1170 , vss => vss
1171 );
1172
1173 p_sdram_we_n : cmpt_gpio
1174 port map ( i => chip_dummy_57
1175 , oe => sdram_we_n_enable_to_pad
1176 , o => sdram_we_n_to_pad
1177 , pad => sdram_we_n
1178 , iovdd => iovdd
1179 , iovss => iovss
1180 , vdd => vdd
1181 , vss => vss
1182 );
1183
1184 p_sdram_a_6 : cmpt_gpio
1185 port map ( i => chip_dummy_47
1186 , oe => sdram_a_6_enable_to_pad
1187 , o => sdram_a_to_pad(6)
1188 , pad => sdram_a(6)
1189 , iovdd => iovdd
1190 , iovss => iovss
1191 , vdd => vdd
1192 , vss => vss
1193 );
1194
1195 p_sdram_a_5 : cmpt_gpio
1196 port map ( i => chip_dummy_46
1197 , oe => sdram_a_5_enable_to_pad
1198 , o => sdram_a_to_pad(5)
1199 , pad => sdram_a(5)
1200 , iovdd => iovdd
1201 , iovss => iovss
1202 , vdd => vdd
1203 , vss => vss
1204 );
1205
1206 p_sdram_a_4 : cmpt_gpio
1207 port map ( i => chip_dummy_45
1208 , oe => sdram_a_4_enable_to_pad
1209 , o => sdram_a_to_pad(4)
1210 , pad => sdram_a(4)
1211 , iovdd => iovdd
1212 , iovss => iovss
1213 , vdd => vdd
1214 , vss => vss
1215 );
1216
1217 p_sdram_a_3 : cmpt_gpio
1218 port map ( i => chip_dummy_44
1219 , oe => sdram_a_3_enable_to_pad
1220 , o => sdram_a_to_pad(3)
1221 , pad => sdram_a(3)
1222 , iovdd => iovdd
1223 , iovss => iovss
1224 , vdd => vdd
1225 , vss => vss
1226 );
1227
1228 p_sdram_a_2 : cmpt_gpio
1229 port map ( i => chip_dummy_43
1230 , oe => sdram_a_2_enable_to_pad
1231 , o => sdram_a_to_pad(2)
1232 , pad => sdram_a(2)
1233 , iovdd => iovdd
1234 , iovss => iovss
1235 , vdd => vdd
1236 , vss => vss
1237 );
1238
1239 p_sdram_a_1 : cmpt_gpio
1240 port map ( i => chip_dummy_42
1241 , oe => sdram_a_1_enable_to_pad
1242 , o => sdram_a_to_pad(1)
1243 , pad => sdram_a(1)
1244 , iovdd => iovdd
1245 , iovss => iovss
1246 , vdd => vdd
1247 , vss => vss
1248 );
1249
1250 p_sdram_a_0 : cmpt_gpio
1251 port map ( i => chip_dummy_41
1252 , oe => sdram_a_0_enable_to_pad
1253 , o => sdram_a_to_pad(0)
1254 , pad => sdram_a(0)
1255 , iovdd => iovdd
1256 , iovss => iovss
1257 , vdd => vdd
1258 , vss => vss
1259 );
1260
1261 p_sdram_a_9 : cmpt_gpio
1262 port map ( i => chip_dummy_50
1263 , oe => sdram_a_9_enable_to_pad
1264 , o => sdram_a_to_pad(9)
1265 , pad => sdram_a(9)
1266 , iovdd => iovdd
1267 , iovss => iovss
1268 , vdd => vdd
1269 , vss => vss
1270 );
1271
1272 p_sdram_a_8 : cmpt_gpio
1273 port map ( i => chip_dummy_49
1274 , oe => sdram_a_8_enable_to_pad
1275 , o => sdram_a_to_pad(8)
1276 , pad => sdram_a(8)
1277 , iovdd => iovdd
1278 , iovss => iovss
1279 , vdd => vdd
1280 , vss => vss
1281 );
1282
1283 p_sdram_a_7 : cmpt_gpio
1284 port map ( i => chip_dummy_48
1285 , oe => sdram_a_7_enable_to_pad
1286 , o => sdram_a_to_pad(7)
1287 , pad => sdram_a(7)
1288 , iovdd => iovdd
1289 , iovss => iovss
1290 , vdd => vdd
1291 , vss => vss
1292 );
1293
1294 p_jtag_tms : cmpt_gpio
1295 port map ( i => jtag_tms_from_pad
1296 , oe => jtag_tms_enable_to_pad
1297 , o => chip_dummy_5
1298 , pad => jtag_tms
1299 , iovdd => iovdd
1300 , iovss => iovss
1301 , vdd => vdd
1302 , vss => vss
1303 );
1304
1305 p_sdram_cke : cmpt_gpio
1306 port map ( i => chip_dummy_54
1307 , oe => sdram_cke_enable_to_pad
1308 , o => sdram_cke_to_pad
1309 , pad => sdram_cke
1310 , iovdd => iovdd
1311 , iovss => iovss
1312 , vdd => vdd
1313 , vss => vss
1314 );
1315
1316 cmpt_corona : corona
1317 port map ( eint_0_from_pad => eint_0_from_pad
1318 , eint_1_from_pad => eint_1_from_pad
1319 , eint_2_from_pad => eint_2_from_pad
1320 , i2c_sda_i_from_pad => i2c_sda_i_from_pad
1321 , jtag_tck_from_pad => jtag_tck_from_pad
1322 , jtag_tdi_from_pad => jtag_tdi_from_pad
1323 , jtag_tms_from_pad => jtag_tms_from_pad
1324 , spimaster_miso_from_pad => spimaster_miso_from_pad
1325 , sys_clk_from_pad => sys_clk_from_pad
1326 , sys_rst_from_pad => sys_rst_from_pad
1327 , uart_rx_from_pad => uart_rx_from_pad
1328 , uart_tx_from_pad => uart_tx_from_pad
1329 , gpio_i_from_pad => gpio_i_from_pad(15 downto 0)
1330 , sdram_dq_i_from_pad => sdram_dq_i_from_pad(15 downto 0)
1331 , nc_from_pad => nc_from_pad(39 downto 0)
1332 , eint_0_enable_to_pad => eint_0_enable_to_pad
1333 , eint_1_enable_to_pad => eint_1_enable_to_pad
1334 , eint_2_enable_to_pad => eint_2_enable_to_pad
1335 , i2c_scl_enable_to_pad => i2c_scl_enable_to_pad
1336 , i2c_scl_to_pad => i2c_scl_to_pad
1337 , i2c_sda_o_to_pad => i2c_sda_o_to_pad
1338 , i2c_sda_oe_to_pad => i2c_sda_oe_to_pad
1339 , jtag_tck_enable_to_pad => jtag_tck_enable_to_pad
1340 , jtag_tdi_enable_to_pad => jtag_tdi_enable_to_pad
1341 , jtag_tdo_enable_to_pad => jtag_tdo_enable_to_pad
1342 , jtag_tdo_to_pad => jtag_tdo_to_pad
1343 , jtag_tms_enable_to_pad => jtag_tms_enable_to_pad
1344 , nc_0_enable_to_pad => nc_0_enable_to_pad
1345 , nc_10_enable_to_pad => nc_10_enable_to_pad
1346 , nc_11_enable_to_pad => nc_11_enable_to_pad
1347 , nc_12_enable_to_pad => nc_12_enable_to_pad
1348 , nc_13_enable_to_pad => nc_13_enable_to_pad
1349 , nc_14_enable_to_pad => nc_14_enable_to_pad
1350 , nc_15_enable_to_pad => nc_15_enable_to_pad
1351 , nc_16_enable_to_pad => nc_16_enable_to_pad
1352 , nc_17_enable_to_pad => nc_17_enable_to_pad
1353 , nc_18_enable_to_pad => nc_18_enable_to_pad
1354 , nc_19_enable_to_pad => nc_19_enable_to_pad
1355 , nc_1_enable_to_pad => nc_1_enable_to_pad
1356 , nc_20_enable_to_pad => nc_20_enable_to_pad
1357 , nc_21_enable_to_pad => nc_21_enable_to_pad
1358 , nc_22_enable_to_pad => nc_22_enable_to_pad
1359 , nc_23_enable_to_pad => nc_23_enable_to_pad
1360 , nc_24_enable_to_pad => nc_24_enable_to_pad
1361 , nc_25_enable_to_pad => nc_25_enable_to_pad
1362 , nc_26_enable_to_pad => nc_26_enable_to_pad
1363 , nc_27_enable_to_pad => nc_27_enable_to_pad
1364 , nc_28_enable_to_pad => nc_28_enable_to_pad
1365 , nc_29_enable_to_pad => nc_29_enable_to_pad
1366 , nc_2_enable_to_pad => nc_2_enable_to_pad
1367 , nc_30_enable_to_pad => nc_30_enable_to_pad
1368 , nc_31_enable_to_pad => nc_31_enable_to_pad
1369 , nc_32_enable_to_pad => nc_32_enable_to_pad
1370 , nc_33_enable_to_pad => nc_33_enable_to_pad
1371 , nc_34_enable_to_pad => nc_34_enable_to_pad
1372 , nc_35_enable_to_pad => nc_35_enable_to_pad
1373 , nc_36_enable_to_pad => nc_36_enable_to_pad
1374 , nc_37_enable_to_pad => nc_37_enable_to_pad
1375 , nc_38_enable_to_pad => nc_38_enable_to_pad
1376 , nc_39_enable_to_pad => nc_39_enable_to_pad
1377 , nc_3_enable_to_pad => nc_3_enable_to_pad
1378 , nc_4_enable_to_pad => nc_4_enable_to_pad
1379 , nc_5_enable_to_pad => nc_5_enable_to_pad
1380 , nc_6_enable_to_pad => nc_6_enable_to_pad
1381 , nc_7_enable_to_pad => nc_7_enable_to_pad
1382 , nc_8_enable_to_pad => nc_8_enable_to_pad
1383 , nc_9_enable_to_pad => nc_9_enable_to_pad
1384 , sdram_a_0_enable_to_pad => sdram_a_0_enable_to_pad
1385 , sdram_a_10_enable_to_pad => sdram_a_10_enable_to_pad
1386 , sdram_a_11_enable_to_pad => sdram_a_11_enable_to_pad
1387 , sdram_a_12_enable_to_pad => sdram_a_12_enable_to_pad
1388 , sdram_a_1_enable_to_pad => sdram_a_1_enable_to_pad
1389 , sdram_a_2_enable_to_pad => sdram_a_2_enable_to_pad
1390 , sdram_a_3_enable_to_pad => sdram_a_3_enable_to_pad
1391 , sdram_a_4_enable_to_pad => sdram_a_4_enable_to_pad
1392 , sdram_a_5_enable_to_pad => sdram_a_5_enable_to_pad
1393 , sdram_a_6_enable_to_pad => sdram_a_6_enable_to_pad
1394 , sdram_a_7_enable_to_pad => sdram_a_7_enable_to_pad
1395 , sdram_a_8_enable_to_pad => sdram_a_8_enable_to_pad
1396 , sdram_a_9_enable_to_pad => sdram_a_9_enable_to_pad
1397 , sdram_ba_0_enable_to_pad => sdram_ba_0_enable_to_pad
1398 , sdram_ba_1_enable_to_pad => sdram_ba_1_enable_to_pad
1399 , sdram_cas_n_enable_to_pad => sdram_cas_n_enable_to_pad
1400 , sdram_cas_n_to_pad => sdram_cas_n_to_pad
1401 , sdram_cke_enable_to_pad => sdram_cke_enable_to_pad
1402 , sdram_cke_to_pad => sdram_cke_to_pad
1403 , sdram_clock_enable_to_pad => sdram_clock_enable_to_pad
1404 , sdram_clock_to_pad => sdram_clock_to_pad
1405 , sdram_cs_n_enable_to_pad => sdram_cs_n_enable_to_pad
1406 , sdram_cs_n_to_pad => sdram_cs_n_to_pad
1407 , sdram_dm_0_enable_to_pad => sdram_dm_0_enable_to_pad
1408 , sdram_dm_1_enable_to_pad => sdram_dm_1_enable_to_pad
1409 , sdram_ras_n_enable_to_pad => sdram_ras_n_enable_to_pad
1410 , sdram_ras_n_to_pad => sdram_ras_n_to_pad
1411 , sdram_we_n_enable_to_pad => sdram_we_n_enable_to_pad
1412 , sdram_we_n_to_pad => sdram_we_n_to_pad
1413 , spimaster_clk_enable_to_pad => spimaster_clk_enable_to_pad
1414 , spimaster_clk_to_pad => spimaster_clk_to_pad
1415 , spimaster_cs_n_enable_to_pad => spimaster_cs_n_enable_to_pad
1416 , spimaster_cs_n_to_pad => spimaster_cs_n_to_pad
1417 , spimaster_miso_enable_to_pad => spimaster_miso_enable_to_pad
1418 , spimaster_mosi_enable_to_pad => spimaster_mosi_enable_to_pad
1419 , spimaster_mosi_to_pad => spimaster_mosi_to_pad
1420 , sys_clk_enable_to_pad => sys_clk_enable_to_pad
1421 , sys_rst_enable_to_pad => sys_rst_enable_to_pad
1422 , uart_rx_enable_to_pad => uart_rx_enable_to_pad
1423 , uart_tx_enable_to_pad => uart_tx_enable_to_pad
1424 , sdram_ba_to_pad => sdram_ba_to_pad(1 downto 0)
1425 , sdram_dm_to_pad => sdram_dm_to_pad(1 downto 0)
1426 , sdram_a_to_pad => sdram_a_to_pad(12 downto 0)
1427 , gpio_o_to_pad => gpio_o_to_pad(15 downto 0)
1428 , gpio_oe_to_pad => gpio_oe_to_pad(15 downto 0)
1429 , sdram_dq_o_to_pad => sdram_dq_o_to_pad(15 downto 0)
1430 , sdram_dq_oe_to_pad => sdram_dq_oe_to_pad(15 downto 0)
1431 , vdd => vdd
1432 , vss => vss
1433 );
1434
1435 p_gpio_7 : cmpt_gpio
1436 port map ( i => gpio_o_to_pad(7)
1437 , oe => gpio_oe_to_pad(7)
1438 , o => gpio_i_from_pad(7)
1439 , pad => gpio_7
1440 , iovdd => iovdd
1441 , iovss => iovss
1442 , vdd => vdd
1443 , vss => vss
1444 );
1445
1446 p_gpio_6 : cmpt_gpio
1447 port map ( i => gpio_o_to_pad(6)
1448 , oe => gpio_oe_to_pad(6)
1449 , o => gpio_i_from_pad(6)
1450 , pad => gpio_6
1451 , iovdd => iovdd
1452 , iovss => iovss
1453 , vdd => vdd
1454 , vss => vss
1455 );
1456
1457 p_gpio_5 : cmpt_gpio
1458 port map ( i => gpio_o_to_pad(5)
1459 , oe => gpio_oe_to_pad(5)
1460 , o => gpio_i_from_pad(5)
1461 , pad => gpio_5
1462 , iovdd => iovdd
1463 , iovss => iovss
1464 , vdd => vdd
1465 , vss => vss
1466 );
1467
1468 p_gpio_4 : cmpt_gpio
1469 port map ( i => gpio_o_to_pad(4)
1470 , oe => gpio_oe_to_pad(4)
1471 , o => gpio_i_from_pad(4)
1472 , pad => gpio_4
1473 , iovdd => iovdd
1474 , iovss => iovss
1475 , vdd => vdd
1476 , vss => vss
1477 );
1478
1479 p_gpio_3 : cmpt_gpio
1480 port map ( i => gpio_o_to_pad(3)
1481 , oe => gpio_oe_to_pad(3)
1482 , o => gpio_i_from_pad(3)
1483 , pad => gpio_3
1484 , iovdd => iovdd
1485 , iovss => iovss
1486 , vdd => vdd
1487 , vss => vss
1488 );
1489
1490 p_gpio_2 : cmpt_gpio
1491 port map ( i => gpio_o_to_pad(2)
1492 , oe => gpio_oe_to_pad(2)
1493 , o => gpio_i_from_pad(2)
1494 , pad => gpio_2
1495 , iovdd => iovdd
1496 , iovss => iovss
1497 , vdd => vdd
1498 , vss => vss
1499 );
1500
1501 p_gpio_1 : cmpt_gpio
1502 port map ( i => gpio_o_to_pad(1)
1503 , oe => gpio_oe_to_pad(1)
1504 , o => gpio_i_from_pad(1)
1505 , pad => gpio_1
1506 , iovdd => iovdd
1507 , iovss => iovss
1508 , vdd => vdd
1509 , vss => vss
1510 );
1511
1512 p_gpio_0 : cmpt_gpio
1513 port map ( i => gpio_o_to_pad(0)
1514 , oe => gpio_oe_to_pad(0)
1515 , o => gpio_i_from_pad(0)
1516 , pad => gpio_0
1517 , iovdd => iovdd
1518 , iovss => iovss
1519 , vdd => vdd
1520 , vss => vss
1521 );
1522
1523 p_sdram_clock : cmpt_gpio
1524 port map ( i => chip_dummy_53
1525 , oe => sdram_clock_enable_to_pad
1526 , o => sdram_clock_to_pad
1527 , pad => sdram_clock
1528 , iovdd => iovdd
1529 , iovss => iovss
1530 , vdd => vdd
1531 , vss => vss
1532 );
1533
1534 p_gpio_9 : cmpt_gpio
1535 port map ( i => gpio_o_to_pad(9)
1536 , oe => gpio_oe_to_pad(9)
1537 , o => gpio_i_from_pad(9)
1538 , pad => gpio_9
1539 , iovdd => iovdd
1540 , iovss => iovss
1541 , vdd => vdd
1542 , vss => vss
1543 );
1544
1545 p_gpio_8 : cmpt_gpio
1546 port map ( i => gpio_o_to_pad(8)
1547 , oe => gpio_oe_to_pad(8)
1548 , o => gpio_i_from_pad(8)
1549 , pad => gpio_8
1550 , iovdd => iovdd
1551 , iovss => iovss
1552 , vdd => vdd
1553 , vss => vss
1554 );
1555
1556 p_sdram_dq_15 : cmpt_gpio
1557 port map ( i => sdram_dq_o_to_pad(15)
1558 , oe => sdram_dq_oe_to_pad(15)
1559 , o => sdram_dq_i_from_pad(15)
1560 , pad => sdram_dq_15
1561 , iovdd => iovdd
1562 , iovss => iovss
1563 , vdd => vdd
1564 , vss => vss
1565 );
1566
1567 p_sdram_dq_14 : cmpt_gpio
1568 port map ( i => sdram_dq_o_to_pad(14)
1569 , oe => sdram_dq_oe_to_pad(14)
1570 , o => sdram_dq_i_from_pad(14)
1571 , pad => sdram_dq_14
1572 , iovdd => iovdd
1573 , iovss => iovss
1574 , vdd => vdd
1575 , vss => vss
1576 );
1577
1578 p_sdram_dq_13 : cmpt_gpio
1579 port map ( i => sdram_dq_o_to_pad(13)
1580 , oe => sdram_dq_oe_to_pad(13)
1581 , o => sdram_dq_i_from_pad(13)
1582 , pad => sdram_dq_13
1583 , iovdd => iovdd
1584 , iovss => iovss
1585 , vdd => vdd
1586 , vss => vss
1587 );
1588
1589 p_sdram_dq_12 : cmpt_gpio
1590 port map ( i => sdram_dq_o_to_pad(12)
1591 , oe => sdram_dq_oe_to_pad(12)
1592 , o => sdram_dq_i_from_pad(12)
1593 , pad => sdram_dq_12
1594 , iovdd => iovdd
1595 , iovss => iovss
1596 , vdd => vdd
1597 , vss => vss
1598 );
1599
1600 p_sdram_dq_11 : cmpt_gpio
1601 port map ( i => sdram_dq_o_to_pad(11)
1602 , oe => sdram_dq_oe_to_pad(11)
1603 , o => sdram_dq_i_from_pad(11)
1604 , pad => sdram_dq_11
1605 , iovdd => iovdd
1606 , iovss => iovss
1607 , vdd => vdd
1608 , vss => vss
1609 );
1610
1611 p_sdram_dq_10 : cmpt_gpio
1612 port map ( i => sdram_dq_o_to_pad(10)
1613 , oe => sdram_dq_oe_to_pad(10)
1614 , o => sdram_dq_i_from_pad(10)
1615 , pad => sdram_dq_10
1616 , iovdd => iovdd
1617 , iovss => iovss
1618 , vdd => vdd
1619 , vss => vss
1620 );
1621
1622 p_eint_0 : cmpt_gpio
1623 port map ( i => eint_0_from_pad
1624 , oe => eint_0_enable_to_pad
1625 , o => chip_dummy_14
1626 , pad => eint_0
1627 , iovdd => iovdd
1628 , iovss => iovss
1629 , vdd => vdd
1630 , vss => vss
1631 );
1632
1633 p_eint_1 : cmpt_gpio
1634 port map ( i => eint_1_from_pad
1635 , oe => eint_1_enable_to_pad
1636 , o => chip_dummy_15
1637 , pad => eint_1
1638 , iovdd => iovdd
1639 , iovss => iovss
1640 , vdd => vdd
1641 , vss => vss
1642 );
1643
1644 p_eint_2 : cmpt_gpio
1645 port map ( i => eint_2_from_pad
1646 , oe => eint_2_enable_to_pad
1647 , o => chip_dummy_16
1648 , pad => eint_2
1649 , iovdd => iovdd
1650 , iovss => iovss
1651 , vdd => vdd
1652 , vss => vss
1653 );
1654
1655 nc_10 : cmpt_gpio
1656 port map ( i => nc_from_pad(10)
1657 , oe => nc_10_enable_to_pad
1658 , o => chip_dummy_21
1659 , pad => nc(10)
1660 , iovdd => iovdd
1661 , iovss => iovss
1662 , vdd => vdd
1663 , vss => vss
1664 );
1665
1666 nc_11 : cmpt_gpio
1667 port map ( i => nc_from_pad(11)
1668 , oe => nc_11_enable_to_pad
1669 , o => chip_dummy_22
1670 , pad => nc(11)
1671 , iovdd => iovdd
1672 , iovss => iovss
1673 , vdd => vdd
1674 , vss => vss
1675 );
1676
1677 nc_12 : cmpt_gpio
1678 port map ( i => nc_from_pad(12)
1679 , oe => nc_12_enable_to_pad
1680 , o => chip_dummy_23
1681 , pad => nc(12)
1682 , iovdd => iovdd
1683 , iovss => iovss
1684 , vdd => vdd
1685 , vss => vss
1686 );
1687
1688 nc_13 : cmpt_gpio
1689 port map ( i => nc_from_pad(13)
1690 , oe => nc_13_enable_to_pad
1691 , o => chip_dummy_24
1692 , pad => nc(13)
1693 , iovdd => iovdd
1694 , iovss => iovss
1695 , vdd => vdd
1696 , vss => vss
1697 );
1698
1699 nc_14 : cmpt_gpio
1700 port map ( i => nc_from_pad(14)
1701 , oe => nc_14_enable_to_pad
1702 , o => chip_dummy_25
1703 , pad => nc(14)
1704 , iovdd => iovdd
1705 , iovss => iovss
1706 , vdd => vdd
1707 , vss => vss
1708 );
1709
1710 nc_15 : cmpt_gpio
1711 port map ( i => nc_from_pad(15)
1712 , oe => nc_15_enable_to_pad
1713 , o => chip_dummy_26
1714 , pad => nc(15)
1715 , iovdd => iovdd
1716 , iovss => iovss
1717 , vdd => vdd
1718 , vss => vss
1719 );
1720
1721 nc_16 : cmpt_gpio
1722 port map ( i => nc_from_pad(16)
1723 , oe => nc_16_enable_to_pad
1724 , o => chip_dummy_27
1725 , pad => nc(16)
1726 , iovdd => iovdd
1727 , iovss => iovss
1728 , vdd => vdd
1729 , vss => vss
1730 );
1731
1732 nc_17 : cmpt_gpio
1733 port map ( i => nc_from_pad(17)
1734 , oe => nc_17_enable_to_pad
1735 , o => chip_dummy_28
1736 , pad => nc(17)
1737 , iovdd => iovdd
1738 , iovss => iovss
1739 , vdd => vdd
1740 , vss => vss
1741 );
1742
1743 nc_18 : cmpt_gpio
1744 port map ( i => nc_from_pad(18)
1745 , oe => nc_18_enable_to_pad
1746 , o => chip_dummy_29
1747 , pad => nc(18)
1748 , iovdd => iovdd
1749 , iovss => iovss
1750 , vdd => vdd
1751 , vss => vss
1752 );
1753
1754 nc_19 : cmpt_gpio
1755 port map ( i => nc_from_pad(19)
1756 , oe => nc_19_enable_to_pad
1757 , o => chip_dummy_30
1758 , pad => nc(19)
1759 , iovdd => iovdd
1760 , iovss => iovss
1761 , vdd => vdd
1762 , vss => vss
1763 );
1764
1765 p_sdram_cas_n : cmpt_gpio
1766 port map ( i => chip_dummy_56
1767 , oe => sdram_cas_n_enable_to_pad
1768 , o => sdram_cas_n_to_pad
1769 , pad => sdram_cas_n
1770 , iovdd => iovdd
1771 , iovss => iovss
1772 , vdd => vdd
1773 , vss => vss
1774 );
1775
1776 p_iovdd_0 : cmpt_iovdd
1777 port map ( iovdd => iovdd
1778 , iovss => iovss
1779 , vdd => vdd
1780 , vss => vss
1781 );
1782
1783 p_iovdd_2 : cmpt_iovdd
1784 port map ( iovdd => iovdd
1785 , iovss => iovss
1786 , vdd => vdd
1787 , vss => vss
1788 );
1789
1790 p_iovdd_1 : cmpt_iovdd
1791 port map ( iovdd => iovdd
1792 , iovss => iovss
1793 , vdd => vdd
1794 , vss => vss
1795 );
1796
1797 nc_29 : cmpt_gpio
1798 port map ( i => nc_from_pad(29)
1799 , oe => nc_29_enable_to_pad
1800 , o => chip_dummy_59
1801 , pad => nc(29)
1802 , iovdd => iovdd
1803 , iovss => iovss
1804 , vdd => vdd
1805 , vss => vss
1806 );
1807
1808 nc_20 : cmpt_gpio
1809 port map ( i => nc_from_pad(20)
1810 , oe => nc_20_enable_to_pad
1811 , o => chip_dummy_31
1812 , pad => nc(20)
1813 , iovdd => iovdd
1814 , iovss => iovss
1815 , vdd => vdd
1816 , vss => vss
1817 );
1818
1819 nc_21 : cmpt_gpio
1820 port map ( i => nc_from_pad(21)
1821 , oe => nc_21_enable_to_pad
1822 , o => chip_dummy_32
1823 , pad => nc(21)
1824 , iovdd => iovdd
1825 , iovss => iovss
1826 , vdd => vdd
1827 , vss => vss
1828 );
1829
1830 nc_22 : cmpt_gpio
1831 port map ( i => nc_from_pad(22)
1832 , oe => nc_22_enable_to_pad
1833 , o => chip_dummy_33
1834 , pad => nc(22)
1835 , iovdd => iovdd
1836 , iovss => iovss
1837 , vdd => vdd
1838 , vss => vss
1839 );
1840
1841 nc_23 : cmpt_gpio
1842 port map ( i => nc_from_pad(23)
1843 , oe => nc_23_enable_to_pad
1844 , o => chip_dummy_34
1845 , pad => nc(23)
1846 , iovdd => iovdd
1847 , iovss => iovss
1848 , vdd => vdd
1849 , vss => vss
1850 );
1851
1852 nc_24 : cmpt_gpio
1853 port map ( i => nc_from_pad(24)
1854 , oe => nc_24_enable_to_pad
1855 , o => chip_dummy_35
1856 , pad => nc(24)
1857 , iovdd => iovdd
1858 , iovss => iovss
1859 , vdd => vdd
1860 , vss => vss
1861 );
1862
1863 nc_25 : cmpt_gpio
1864 port map ( i => nc_from_pad(25)
1865 , oe => nc_25_enable_to_pad
1866 , o => chip_dummy_36
1867 , pad => nc(25)
1868 , iovdd => iovdd
1869 , iovss => iovss
1870 , vdd => vdd
1871 , vss => vss
1872 );
1873
1874 nc_26 : cmpt_gpio
1875 port map ( i => nc_from_pad(26)
1876 , oe => nc_26_enable_to_pad
1877 , o => chip_dummy_37
1878 , pad => nc(26)
1879 , iovdd => iovdd
1880 , iovss => iovss
1881 , vdd => vdd
1882 , vss => vss
1883 );
1884
1885 nc_27 : cmpt_gpio
1886 port map ( i => nc_from_pad(27)
1887 , oe => nc_27_enable_to_pad
1888 , o => chip_dummy_38
1889 , pad => nc(27)
1890 , iovdd => iovdd
1891 , iovss => iovss
1892 , vdd => vdd
1893 , vss => vss
1894 );
1895
1896 nc_28 : cmpt_gpio
1897 port map ( i => nc_from_pad(28)
1898 , oe => nc_28_enable_to_pad
1899 , o => chip_dummy_39
1900 , pad => nc(28)
1901 , iovdd => iovdd
1902 , iovss => iovss
1903 , vdd => vdd
1904 , vss => vss
1905 );
1906
1907 end structural;
1908