3 from nmigen
.back
.pysim
import *
6 from ..csr
.wishbone
import *
9 class MockRegister(Elaboratable
):
10 def __init__(self
, width
):
11 self
.element
= csr
.Element(width
, "rw")
12 self
.r_count
= Signal(8)
13 self
.w_count
= Signal(8)
14 self
.data
= Signal(width
)
16 def elaborate(self
, platform
):
19 with m
.If(self
.element
.r_stb
):
20 m
.d
.sync
+= self
.r_count
.eq(self
.r_count
+ 1)
21 m
.d
.comb
+= self
.element
.r_data
.eq(self
.data
)
23 with m
.If(self
.element
.w_stb
):
24 m
.d
.sync
+= self
.w_count
.eq(self
.w_count
+ 1)
25 m
.d
.sync
+= self
.data
.eq(self
.element
.w_data
)
30 class WishboneCSRBridgeTestCase(unittest
.TestCase
):
31 def test_wrong_csr_bus(self
):
32 with self
.assertRaisesRegex(ValueError,
33 r
"CSR bus must be an instance of CSRInterface, not 'foo'"):
34 WishboneCSRBridge(csr_bus
="foo")
36 def test_wrong_csr_bus_data_width(self
):
37 with self
.assertRaisesRegex(ValueError,
38 r
"CSR bus data width must be one of 8, 16, 32, 64, not 7"):
39 WishboneCSRBridge(csr_bus
=csr
.Interface(addr_width
=10, data_width
=7))
41 def test_narrow(self
):
42 mux
= csr
.Multiplexer(addr_width
=10, data_width
=8)
43 reg_1
= MockRegister(8)
44 mux
.add(reg_1
.element
)
45 reg_2
= MockRegister(16)
46 mux
.add(reg_2
.element
)
47 dut
= WishboneCSRBridge(mux
.bus
)
50 yield dut
.wb_bus
.cyc
.eq(1)
51 yield dut
.wb_bus
.sel
.eq(0b1)
53 yield dut
.wb_bus
.we
.eq(1)
55 yield dut
.wb_bus
.adr
.eq(0)
56 yield dut
.wb_bus
.stb
.eq(1)
57 yield dut
.wb_bus
.dat_w
.eq(0x55)
60 yield dut
.wb_bus
.stb
.eq(0)
62 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
63 self
.assertEqual((yield reg_1
.r_count
), 0)
64 self
.assertEqual((yield reg_1
.w_count
), 1)
65 self
.assertEqual((yield reg_1
.data
), 0x55)
67 yield dut
.wb_bus
.adr
.eq(1)
68 yield dut
.wb_bus
.stb
.eq(1)
69 yield dut
.wb_bus
.dat_w
.eq(0xaa)
72 yield dut
.wb_bus
.stb
.eq(0)
74 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
75 self
.assertEqual((yield reg_2
.r_count
), 0)
76 self
.assertEqual((yield reg_2
.w_count
), 0)
77 self
.assertEqual((yield reg_2
.data
), 0)
79 yield dut
.wb_bus
.adr
.eq(2)
80 yield dut
.wb_bus
.stb
.eq(1)
81 yield dut
.wb_bus
.dat_w
.eq(0xbb)
84 yield dut
.wb_bus
.stb
.eq(0)
86 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
87 self
.assertEqual((yield reg_2
.r_count
), 0)
88 self
.assertEqual((yield reg_2
.w_count
), 1)
89 self
.assertEqual((yield reg_2
.data
), 0xbbaa)
91 yield dut
.wb_bus
.we
.eq(0)
93 yield dut
.wb_bus
.adr
.eq(0)
94 yield dut
.wb_bus
.stb
.eq(1)
97 yield dut
.wb_bus
.stb
.eq(0)
99 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
100 self
.assertEqual((yield dut
.wb_bus
.dat_r
), 0x55)
101 self
.assertEqual((yield reg_1
.r_count
), 1)
102 self
.assertEqual((yield reg_1
.w_count
), 1)
104 yield dut
.wb_bus
.adr
.eq(1)
105 yield dut
.wb_bus
.stb
.eq(1)
108 yield dut
.wb_bus
.stb
.eq(0)
110 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
111 self
.assertEqual((yield dut
.wb_bus
.dat_r
), 0xaa)
112 self
.assertEqual((yield reg_2
.r_count
), 1)
113 self
.assertEqual((yield reg_2
.w_count
), 1)
115 yield reg_2
.data
.eq(0x33333)
117 yield dut
.wb_bus
.adr
.eq(2)
118 yield dut
.wb_bus
.stb
.eq(1)
121 yield dut
.wb_bus
.stb
.eq(0)
123 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
124 self
.assertEqual((yield dut
.wb_bus
.dat_r
), 0xbb)
125 self
.assertEqual((yield reg_2
.r_count
), 1)
126 self
.assertEqual((yield reg_2
.w_count
), 1)
129 m
.submodules
+= mux
, reg_1
, reg_2
, dut
130 with
Simulator(m
, vcd_file
=open("test.vcd", "w")) as sim
:
132 sim
.add_sync_process(sim_test())
136 mux
= csr
.Multiplexer(addr_width
=10, data_width
=8)
137 reg
= MockRegister(32)
139 dut
= WishboneCSRBridge(mux
.bus
, data_width
=32)
142 yield dut
.wb_bus
.cyc
.eq(1)
143 yield dut
.wb_bus
.adr
.eq(0)
145 yield dut
.wb_bus
.we
.eq(1)
147 yield dut
.wb_bus
.dat_w
.eq(0x44332211)
148 yield dut
.wb_bus
.sel
.eq(0b1111)
149 yield dut
.wb_bus
.stb
.eq(1)
155 yield dut
.wb_bus
.stb
.eq(0)
157 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
158 self
.assertEqual((yield reg
.r_count
), 0)
159 self
.assertEqual((yield reg
.w_count
), 1)
160 self
.assertEqual((yield reg
.data
), 0x44332211)
163 yield dut
.wb_bus
.dat_w
.eq(0xaabbccdd)
164 yield dut
.wb_bus
.sel
.eq(0b0110)
165 yield dut
.wb_bus
.stb
.eq(1)
171 yield dut
.wb_bus
.stb
.eq(0)
173 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
174 self
.assertEqual((yield reg
.r_count
), 0)
175 self
.assertEqual((yield reg
.w_count
), 1)
176 self
.assertEqual((yield reg
.data
), 0x44332211)
178 yield dut
.wb_bus
.we
.eq(0)
180 yield dut
.wb_bus
.sel
.eq(0b1111)
181 yield dut
.wb_bus
.stb
.eq(1)
187 yield dut
.wb_bus
.stb
.eq(0)
189 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
190 self
.assertEqual((yield dut
.wb_bus
.dat_r
), 0x44332211)
191 self
.assertEqual((yield reg
.r_count
), 1)
192 self
.assertEqual((yield reg
.w_count
), 1)
194 yield reg
.data
.eq(0xaaaaaaaa)
197 yield dut
.wb_bus
.sel
.eq(0b0110)
198 yield dut
.wb_bus
.stb
.eq(1)
204 yield dut
.wb_bus
.stb
.eq(0)
206 self
.assertEqual((yield dut
.wb_bus
.ack
), 1)
207 self
.assertEqual((yield dut
.wb_bus
.dat_r
), 0x00332200)
208 self
.assertEqual((yield reg
.r_count
), 1)
209 self
.assertEqual((yield reg
.w_count
), 1)
212 m
.submodules
+= mux
, reg
, dut
213 with
Simulator(m
, vcd_file
=open("test.vcd", "w")) as sim
:
215 sim
.add_sync_process(sim_test())