openpower/sv/rfc/ls007.mdwn

   1 # RFC ls007 Ternary/Binary GPR and CR Field bit-operations
   2
   3 **URLs**:
   4
   5 * <https://libre-soc.org/openpower/sv/bitmanip/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls007/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1017>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/todo>
   9
  10 **Severity**: Major
  11
  12 **Status**: New
  13
  14 **Date**: 20 Oct 2022
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.1B
  19
  20 **Books and Section affected**: **UPDATE**
  21
  22 * Book I 2.5.1 Condition Register Logical Instructions
  23 * Book I 3.3.13 Fixed-Point Logical Instructions
  24 * Appendix E Power ISA sorted by opcode
  25 * Appendix F Power ISA sorted by version
  26 * Appendix G Power ISA sorted by Compliancy Subset
  27 * Appendix H Power ISA sorted by mnemonic
  28
  29 **Summary**
  30
  31 Instructions added
  32
  33 * `ternlogi` -- Ternary Logic Immediate
  34 * `crternlogi` -- Condition Register Ternary Logic Immediate
  35 * `binlog` -- Dynamic Binary Logic
  36 * `crbinlog` -- Condition Register Dynamic Binary Logic
  37
  38 **Submitter**: Luke Leighton (Libre-SOC)
  39
  40 **Requester**: Libre-SOC
  41
  42 **Impact on processor**:
  43
  44 * Addition of two new GPR-based instructions
  45 * Addition of two new CR-field-based instructions
  46
  47 **Impact on software**:
  48
  49 * Requires support for new instructions in assembler, debuggers,
  50   and related tools.
  51
  52 **Keywords**:
  53
  54 ```
  55 GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table
  56 ```
  57
  58 **Motivation**
  59
  60 * `ternlogi` is similar to existing `and`/`or`/`xor`/etc. instructions, but
  61   allows any arbitrary 3-input 1-output bitwise operation. This can be used to
  62   combine several instructions into one. E.g. `A ^ (~B & (C | A))` can become
  63   one instruction. This can also be used to have one instruction for
  64   bitwise MUX `(A & B) | (~A & C)`.
  65 * `binlog` is like `ternlogi` except it supports any arbitrary 2-input
  66   1-output bitwise operation, where the operation can be selected dynamically
  67   at runtime. This operates similarly to LUTs in a FPGA.
  68 * `crternlogi` is like `ternlogi` except it works with CRs instead of GPRs.
  69 * `crbinlog` is like `binlog` except it works with CRs instead of GPRs.
  70
  71 **Notes and Observations**:
  72
  73 * `ternlogi` is like the existing `xxeval` instruction, except operates on
  74   GPRs instead of VSRs and doesn't require VSX/VMX.
  75
  76 **Changes**
  77
  78 Add the following entries to:
  79
  80 * Book I 2.5.1 Condition Register Logical Instructions
  81 * Book I 3.3.13 Fixed-Point Logical Instructions
  82 * Book I 1.6.1 and 1.6.2
  83
  84 ----------------
  85
  86 \newpage{}
  87
  88 # CRB-FORM
  89
  90 Add the following section to Book I 1.6.1
  91
  92 ```
  93 |0   |6   |9    |12   |15   |18   |21   |29  |31   |
  94 | PO | BF | BFA | BFB | BFC | msk | TLI | XO | msk |
  95 ```
  96
  97 # TLI-FORM
  98
  99 Add the following section to Book I 1.6.1
 100
 101 ```
 102 |0   |6   |11  |16  |21   |29  |31  |
 103 | PO | RT | RA | RB | TLI | XO | Rc |
 104 ```
 105
 106 # VA-FORM
 107
 108 Add the following entry to VA-FORM in Book I 1.6.1.12
 109
 110 ```
 111 |0      |6     |11     |16     |21|22    |26|27   |
 112 | PO    |  RT  |   RA  |   RB  |   RC    |nh| XO  |
 113 ```
 114
 115 # Word Instruction Fields
 116
 117 Add the following to Book I 1.6.2
 118
 119 ```
 120 msk (18:20, 31)
 121     Field used by crternlogi to decide which CR bits to modify.
 122     Formats: CRB
 123 ```
 124
 125 ```
 126 nh (26)
 127     Nibble High. Field used by binlog to decide if the look-up-table should
 128     be taken from bits 60:63 or 56:59 of RC.
 129     Formats: VA
 130 ```
 131
 132 ```
 133 TLI (21:28)
 134     Field used by the ternlogi instruction as the
 135     look-up table.
 136     Formats: TLI, CRB
 137 ```
 138
 139 ```
 140 XO (29:30)
 141     Extended opcode field.
 142     Formats: TLI, CRB
 143 ```
 144
 145 Add `TLI` to the `Formats:` list of all of `RA`, `RB`, `RT`, and `Rc`.
 146 Add `CRB` to the `Formats:` list of all of `BF`, `BFA`, `BFB`, and `BFC`.
 147 Add `VA` to the `Formats:` list of `XO (27:31)`.
 148
 149 ----------
 150
 151 \newpage{}
 152
 153 # Ternary Logic Immediate
 154
 155 TLI-form
 156
 157 Add this section to Book I 3.3.13
 158
 159 * `ternlogi RT, RA, RB, TLI` (`Rc=0`)
 160 * `ternlogi. RT, RA, RB, TLI` (`Rc=1`)
 161
 162 | 0-5 | 6-10 | 11-15 | 16-20 | 21-28 | 29-30 | 31 | Form     |
 163 |-----|------|-------|-------|-------|-------|----|----------|
 164 | PO  | RT   |  RA   |  RB   | TLI   | XO    | Rc | TLI-Form |
 165
 166 Pseudocode:
 167
 168 ```
 169 result <- [0] * 64
 170 do i = 0 to 63
 171     idx <- (RT)[i] || (RA)[i] || (RB)[i]  # compute index from current bits
 172     result[i] <- TLI[7 - idx]  # subtract from 7 to index in LSB0 order
 173 RT <- result
 174 ```
 175
 176 Special registers altered:
 177
 178 ```
 179 CR0                    (if Rc=1)
 180 ```
 181
 182 ----------
 183
 184 \newpage{}
 185
 186 # Condition Register Ternary Logic Immediate
 187
 188 CRB-form
 189
 190 Add this section to Book I 2.5.1
 191
 192 * `crternlogi BT, BA, BB, BC, TLI, msk`
 193
 194 | 0.5| 6-8 | 9-11 | 12-14 | 15-17 | 18-20 | 21-28 | 29-30 | 31  | Form     |
 195 |----|-----|------|-------|-------|-------|-------|-------|-----|----------|
 196 | PO | BF  | BFA  | BFB   | BFC   | msk   |  TLI  |  XO   | msk | CRB-Form |
 197
 198 Pseudocode:
 199
 200 ```
 201 a <- CR[4*BFA+32:4*BFA+35]
 202 b <- CR[4*BFB+32:4*BFB+35]
 203 c <- CR[4*BFC+32:4*BFC+35]
 204 do i = 0 to 3
 205     idx <- a[i] || b[i] || c[i]  # compute index from current bits
 206     result <- TLI[7 - idx]  # subtract from 7 to index in LSB0 order
 207     if msk[i] = 1 then
 208         CR[4*BF+32+i] <- result
 209 ```
 210
 211 Special registers altered:
 212
 213 ```
 214 CR field BF
 215 ```
 216
 217 ----------
 218
 219 \newpage{}
 220
 221 # Dynamic Binary Logic
 222
 223 VA-form
 224
 225 Add this section to Book I 3.3.13
 226
 227 * `binlog RT, RA, RB, RC, nh`
 228
 229 | 0-5 | 6-10 | 11-15 | 16-20 | 21-25 | 26 | 27-31 | Form    |
 230 |-----|------|-------|-------|-------|----|-------|---------|
 231 | PO  |  RT  |  RA   |  RB   |  RC   | nh | XO    | VA-Form |
 232
 233 Pseudocode:
 234
 235 ```
 236 if nh = 1 then
 237     lut <- (RC)[56:59]
 238 else
 239     lut <- (RC)[60:63]
 240 do i = 0 to 63
 241     idx <- (RB)[i] || (RA)[i]  # compute index from current bits
 242     result[i] <- lut[3 - idx]  # subtract from 3 to index in LSB0 order
 243 RT <- result
 244 ```
 245
 246 Special registers altered:
 247
 248 ```
 249 None
 250 ```
 251
 252 **Programming Note**:
 253
 254 Dynamic Ternary Logic may be emulated by appropriate combination of `binlog` and `ternlogi`:
 255
 256 ```
 257 # compute r3 = ternlog(r4, r5, r6, table=r7)
 258 # compute the values for when r6[i] = 0:
 259 binlog r3, r4, r5, r7, 0  # takes look-up-table from LSB 4 bits
 260 # compute the values for when r6[i] = 1:
 261 binlog r4, r4, r5, r7, 1  # takes look-up-table from second-to-LSB 4 bits
 262 # mux the two results together: r3 = (r3 & ~r6) | (r4 & r6)
 263 ternlogi r3, r4, r6, 0b11011000
 264 ```
 265
 266 ----------
 267
 268 \newpage{}
 269
 270
 271 ----------
 272
 273 # Appendices
 274
 275     Appendix E Power ISA sorted by opcode
 276     Appendix F Power ISA sorted by version
 277     Appendix G Power ISA sorted by Compliancy Subset
 278     Appendix H Power ISA sorted by mnemonic
 279
 280 |Form| Book | Page | Version | mnemonic | Description |
 281 |----|------|------|---------|----------|-------------|
 282 |TLI | I    | #    | 3.2B    | ternlogi | Ternary Logic Immediate |
 283
 284 ----------------
 285
 286 [[!tag opf_rfc]]