1 # SVP64 Zero-Overhead Loop Prefix Subsystem
4 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[Power|openpower]] v3.0B [[ISA|openpower/isa/]].
9 Credits and acknowledgements:
17 * NLnet Foundation, for funding
18 * OpenPOWER Foundation
21 * IBM for the Power ISA itself
26 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
27 * [[svp64/discussion]]
29 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
30 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
31 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
34 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045> External RFC ls010
35 * [[sv/branches]] chapter
45 Simple-V is a type of Vectorisation best described as a "Prefix Loop
46 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and
47 to the 8086 `REP` Prefix instruction. More advanced features are similar
48 to the Z80 `CPIR` instruction. If naively viewed one-dimensionally as an
49 actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
50 Vector instructions on the SFFS Subset and closer to 10 million 64-bit
51 True-Scalable Vector instructions if introduced on VSX. SVP64, the
52 instruction format used by Simple-V, is therefore best viewed as an
53 orthogonal RISC-paradigm "Prefixing" subsystem instead.
55 Except where explicitly stated all bit numbers remain as in the rest of
56 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
57 the left and counting up as you move rightwards to the LSB end). All bit
58 ranges are inclusive (so `4:6` means bits 4, 5, and 6, in MSB0 order).
59 **All register numbering and element numbering however is LSB0 ordering**
60 which is a different convention from that used elsewhere in the Power ISA.
62 The SVP64 prefix always comes before the suffix in PC order and must be
63 considered an independent "Defined word" that augments the behaviour of
64 the following instruction, but does **not** change the actual Decoding
65 of that following instruction. **All prefixed 32-bit instructions
66 (Defined Words) retain their non-prefixed encoding and definition**.
68 Two apparent exceptions to the above hard rule exist: SV
69 Branch-Conditional operations and LD/ST-update "Post-Increment"
70 Mode. Post-Increment was considered sufficiently high priority
71 (significantly reducing hot-loop instruction count) that one bit in
72 the Prefix is reserved for it (*Note the intention to release that bit
73 and move Post-Increment instructions to EXT2xx, as part of [[ls011]]*).
74 Vectorised Branch-Conditional operations "embed" the original Scalar
75 Branch-Conditional behaviour into a much more advanced variant that is
76 highly suited to High-Performance Computation (HPC), Supercomputing,
77 and parallel GPU Workloads.
79 *Architectural Resource Allocation note: it is prohibited to accept RFCs
80 which fundamentally violate this hard requirement. Under no circumstances
81 must the Suffix space have an alternate instruction encoding allocated
82 within SVP64 that is entirely different from the non-prefixed Defined
83 Word. Hardware Implementors critically rely on this inviolate guarantee
84 to implement High-Performance Multi-Issue micro-architectures that can
85 sustain 100% throughput*
87 Subset implementations in hardware are permitted, as long as certain
88 rules are followed, allowing for full soft-emulation including future
89 revisions. Compliancy Subsets exist to ensure minimum levels of binary
90 interoperability expectations within certain environments. Details in
91 the [[svp64/appendix]].
93 ## SVP64 encoding features
95 A number of features need to be compacted into a very small space of
98 * Independent per-register Scalar/Vector tagging and range extension on
100 * Element width overrides on both source and destination
101 * Predication on both source and destination
102 * Two different sources of predication: INT and CR Fields
103 * SV Modes including saturation (for Audio, Video and DSP), mapreduce,
106 Different classes of operations require different formats. The earlier
107 sections cover the common formats and the four separate modes follow:
108 CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
109 and Branch-Conditional.
111 ## Definition of Reserved in this spec.
113 For the new fields added in SVP64, instructions that have any of their
114 fields set to a reserved value must cause an illegal instruction trap,
115 to allow emulation of future instruction sets, or for subsets of SVP64 to
116 be implemented in hardware and the rest emulated. This includes SVP64
117 SPRs: reading or writing values which are not supported in hardware
118 must also raise illegal instruction traps in order to allow emulation.
119 Unless otherwise stated, reserved values are always all zeros.
121 This is unlike OpenPower ISA v3.1, which in many instances does not
122 require a trap if reserved fields are nonzero. Where the standard Power
123 ISA definition is intended the red keyword `RESERVED` is used.
125 ## Definition of "UnVectoriseable"
127 Any operation that inherently makes no sense if repeated is termed
128 "UnVectoriseable" or "UnVectorised". Examples include `sc` or `sync`
129 which have no registers. `mtmsr` is also classed as UnVectoriseable
130 because there is only one `MSR`.
132 UnVectorised instructions are required to be detected as such if
133 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
136 *Architectural Note: Given that a "pre-classification" Decode Phase is
137 required (identifying whether the Suffix - Defined Word - is
138 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
139 adding "UnVectorised" to this phase is not unreasonable.*
141 ## Definition of Strict Program Order
143 Strict Program Order is defined as giving the appearance, as far
144 as programs are concerned, that instructions were executed
145 strictly in the sequence that they occurred. A "Precise"
147 Micro-architecture goes to considerable lengths to ensure that
150 Many Vector ISAs allow interrupts to occur in the middle of
151 processing of large Vector operations, only under the condition
152 that partial results are cleanly discarded, and continuation on return
153 from the Trap Handler will restart the entire operation.
154 The reason is that saving of full Architectural State is
155 not practical. An example would be a Floating-Point Horizontal Sum instruction
156 (very common in Vector ISAs) or a Dot Product instruction
157 that specifies a higher degree of accuracy for the *internal*
158 accumulator than the registers.
160 Simple-V operates on an entirely different paradigm from traditional
161 Vector ISAs: as a Sub-Program Counter where "Elements" are synonymous
162 with Scalar instructions. With this in mind it is critical for
163 implementations to observe Strict Element-Level Program Order
165 (often simply referred to as just "Strict Program Order"
168 *Any* element is Interruptible and Simple-V has
169 been carefully designed to guarantee that Architectural State may
170 be fully preserved and restored regardless of that same State, but
171 it is not necessarily guaranteed that the amount of time needed to recover
172 will be low latency (particularly if REMAP
175 Interrupts still only save `MSR` and `PC` in `SRR0` and `SRR1`
176 but the full SVP64 Architectural State may be saved and
177 restored through manual copying of `SVSTATE` (and the four
178 REMAP SPRs if in use at the time)
179 Whilst this initially sounds unsafe in reality
180 all that Trap Handlers (and function call stack save/restore)
182 use of SVP64 Prefixed instructions to perform the necessary
183 save/restore of Simple-V Architectural State.
184 This capability also allows nested function calls to be made from
185 inside Vertical-First Vector loops, which is very rare for Vector ISAs.
187 Strict Program Order is also preserved by the Parallel Reduction
188 REMAP Schedule, but only at the cost of requiring the destination
189 Vector to be used (Deterministically) to store partial progress of the
192 The only major caveat for REMAP is that
193 after an explicit change to
194 Architectural State caused by writing to the
195 Simple-V SPRs, some implementations may find
196 it easier to take longer to calculate where in a given Schedule
197 the re-mapping Indices were. Obvious examples include Interrupts occuring
198 in the middle of a non-RADIX2 Matrix Multiply Schedule (5x3 by 3x3
200 will force implementations to perform divide and modulo
203 An additional caveat involves Condition Register Fields
204 when also used as Predicate Masks. An operation that
205 overwrites the same CR Fields that are simultaneously
206 being used as a Predicate Mask should exercise extreme care
207 if the overwritten CR field element was needed by a
208 subsequent Element for its Predicate Mask bit.
210 Some implementations may deploy Cray's technique of
211 "Vector Chaining" (including in this case reading the CR field
212 containing the Predicate bit until the very last moment),
213 and consequently avoiding the risk of
214 overwrite is the responsibility of the Programmer.
215 `hphint` may be used here to good effect.
216 Extra Special care is particularly needed here when using REMAP
217 and also Vertical-First Mode.
219 The simplest option is to use Integer Predicate Masks but the
220 caveats are stricter:
222 * In Vertical-First loops Programmers **must not** write to any
223 Integers (r3, r0, r31) used as Predicate Masks. Doing so
224 is `UNDEFINED` behaviour.
225 * An **entire** Vector is held up on Horizontal-First Mode if the
226 Integer Predicate is still in in-flight Reservation Stations
227 or pipelines. Speculative Vector Chained Execution mitigates delays
228 but can be heavy on Reservation Station resources.
230 ## Register files, elements, and Element-width Overrides
232 The relationship between register files, elements, and element-width
233 overrides is expressed as follows:
235 * register files are considered to be *byte-level* contiguous SRAMs,
236 accessed exclusively in Little-Endian Byte-Order at all times
237 * elements are sequential contiguous unbounded arrays starting at the "address"
238 of any given 64-bit GPR or FPR, numbered from 0 as the first,
239 "spilling" into numerically-sequentially-increasing GPRs
240 * element-width overrides set the width of the *elements* in the
241 sequentially-numbered contiguous array.
243 The relationship is best defined in Canonical form, below, in ANSI c as a
244 union data structure. A key difference is that VSR elements are bounded
245 fixed at 128-bit, where SVP64 elements are conceptually unbounded and
246 only limited by the Maximum Vector Length.
248 *Future specification note: SVP64 may be defined on top of VSRs in future.
249 At which point VSX also gains conceptually unbounded VSR register elements*
251 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR
252 Register files are expanded from 32 to 128 entries, and the number of
253 CR Fields expanded from CR0-CR7 to CR0-CR127. (Note: A future version
254 of SVP64 is anticipated to extend the VSR register file).
256 Memory access remains exactly the same: the effects of `MSR.LE` remain
257 exactly the same, affecting as they already do and remain **only**
258 on the Load and Store memory-register operation byte-order, and having
259 nothing to do with the ordering of the contents of register files or
260 register-register operations.
262 The only major impact on Arithmetic and Logical operations is that all
263 Scalar operations are defined, where practical and workable, to have
264 three new widths: elwidth=32, elwidth=16, elwidth=8. The default of
265 elwidth=64 is the pre-existing (Scalar) behaviour which remains 100%
266 unchanged. Thus, `addi` is now joined by a 32-bit, 16-bit, and 8-bit
267 variant of `addi`, but the sole exclusive difference is the width.
268 *In no way* is the actual `addi` instruction fundamentally altered.
269 FP Operations elwidth overrides are also defined, as explained in
270 the [[svp64/appendix]].
272 To be absolutely clear:
275 There are no conceptual arithmetic ordering or other changes over the
276 Scalar Power ISA definitions to registers or register files or to
277 arithmetic or Logical Operations beyond element-width subdivision
281 numbering is naturally **LSB0-sequentially-incrementing from zero, not
282 MSB0-incrementing** including when element-width overrides are used,
283 at which point the elements progress through each register
284 sequentially from the LSB end
285 (confusingly numbered the highest in MSB0 ordering) and progress
286 incrementally to the MSB end (confusingly numbered the lowest in
289 When exclusively using MSB0-numbering, SVP64 becomes unnecessarily complex
290 to both express and subsequently understand: the required conditional
291 subtractions from 63, 31, 15 and 7 needed to express the fact that
292 elements are LSB0-sequential unfortunately become a hostile minefield,
293 obscuring both intent and meaning. Therefore for the purposes of this
294 section the more natural **LSB0 numbering is assumed** and it is left
295 to the reader to translate to MSB0 numbering.
297 The Canonical specification for how element-sequential numbering and
298 element-width overrides is defined is expressed in the following c
299 structure, assuming a Little-Endian system, and naturally using LSB0
300 numbering everywhere because the ANSI c specification is inherently LSB0.
301 Note the deliberate similarity to how VSX register elements are defined,
302 from Figure 97, Book I, Section 6.3, Page 258:
307 uint8_t actual_bytes[8];
308 // all of these are very deliberately unbounded arrays
309 // that intentionally "wrap" into subsequent actual_bytes...
310 uint8_t bytes[]; // elwidth 8
311 uint16_t hwords[]; // elwidth 16
312 uint32_t words[]; // elwidth 32
313 uint64_t dwords[]; // elwidth 64
317 // ... here, as packed statically-defined GPRs.
318 elreg_t int_regfile[128];
320 // use element 0 as the destination
321 void get_register_element(el_reg_t* el, int gpr, int element, int width) {
323 case 64: el->dwords[0] = int_regfile[gpr].dwords[element];
324 case 32: el->words[0] = int_regfile[gpr].words[element];
325 case 16: el->hwords[0] = int_regfile[gpr].hwords[element];
326 case 8 : el->bytes[0] = int_regfile[gpr].bytes[element];
330 // use element 0 as the source
331 void set_register_element(el_reg_t* el, int gpr, int element, int width) {
333 case 64: int_regfile[gpr].dwords[element] = el->dwords[0];
334 case 32: int_regfile[gpr].words[element] = el->words[0];
335 case 16: int_regfile[gpr].hwords[element] = el->hwords[0];
336 case 8 : int_regfile[gpr].bytes[element] = el->bytes[0];
341 Example Vector-looped add operation implementation when elwidths are 64-bit:
344 # vector-add RT, RA,RB using the "uint64_t" union member, "dwords"
346 int_regfile[RT].dword[i] = int_regfile[RA].dword[i] + int_regfile[RB].dword[i]
349 However if elwidth overrides are set to 16 for both source and destination:
352 # vector-add RT, RA, RB using the "uint64_t" union member "hwords"
354 int_regfile[RT].hwords[i] = int_regfile[RA].hwords[i] + int_regfile[RB].hwords[i]
357 The most fundamental aspect here to understand is that the wrapping
358 into subsequent Scalar GPRs that occurs on larger-numbered elements
359 including and especially on smaller element widths is **deliberate
360 and intentional**. From this Canonical definition it should be clear
361 that sequential elements begin at the LSB end of any given underlying
362 Scalar GPR, progress to the MSB end, and then to the LSB end of the
363 *next numerically-larger Scalar GPR*. In the example above if VL=5
364 and RT=1 then the contents of GPR(1) and GPR(2) will be as follows.
365 For clarity in the table below:
367 * Both MSB0-ordered bitnumbering *and* LSB-ordered bitnumbering are shown
368 * The GPR-numbering is considered LSB0-ordered
369 * The Element-numbering (result0-result4) is LSB0-ordered
370 * Each of the results (result0-result4) are 16-bit
371 * "same" indicates "no change as a result of the Vectorised add"
374 | MSB0: | 0:15 | 16:31 | 32:47 | 48:63 |
375 | LSB0: | 63:48 | 47:32 | 31:16 | 15:0 |
376 |--------|---------|---------|---------|---------|
377 | GPR(0) | same | same | same | same |
378 | GPR(1) | result3 | result2 | result1 | result0 |
379 | GPR(2) | same | same | same | result4 |
380 | GPR(3) | same | same | same | same |
381 | ... | ... | ... | ... | ... |
382 | ... | ... | ... | ... | ... |
385 Note that the upper 48 bits of GPR(2) would **not** be modified due to
386 the example having VL=5. Thus on "wrapping" - sequential progression
387 from GPR(1) into GPR(2) - the 5th result modifies **only** the bottom
390 If the 16-bit operation were to be followed up with a 32-bit Vectorised
391 Operation, the exact same contents would be viewed as follows:
394 | MSB0: | 0:31 | 32:63 |
395 | LSB0: | 63:32 | 31:0 |
396 |--------|----------------------|----------------------|
397 | GPR(0) | same | same |
398 | GPR(1) | (result3 || result2) | (result1 || result0) |
399 | GPR(2) | same | (same || result4) |
400 | GPR(3) | same | same |
405 In other words, this perspective really is no different from the situation
406 where the actual Register File is treated as an Industry-standard
407 byte-level-addressable Little-Endian-addressed SRAM. Note that
408 this perspective does **not** involve `MSR.LE` in any way shape or
409 form because `MSR.LE` is directly in control of the Memory-to-Register
410 byte-ordering. This section is exclusively about how to correctly perceive
411 Simple-V-Augmented **Register** Files.
413 *Engineering note: to avoid a Read-Modify-Write at the register
414 file it is strongly recommended to implement byte-level write-enable lines
415 exactly as has been implemented in DRAM ICs for many decades. Additionally
416 the predicate mask bit is advised to be associated with the element
417 operation and alongside the result ultimately passed to the register file.
418 When element-width is set to 64-bit the relevant predicate mask bit
419 may be repeated eight times and pull all eight write-port byte-level
420 lines HIGH. Clearly when element-width is set to 8-bit the relevant
421 predicate mask bit corresponds directly with one single byte-level
422 write-enable line. It is up to the Hardware Architect to then amortise
423 (merge) elements together into both PredicatedSIMD Pipelines as well
424 as simultaneous non-overlapping Register File writes, to achieve High
425 Performance designs. Overall it helps to think of the GPR and FPR
426 register files as being much more akin to a 64-bit-wide byte-level-addressable SRAM.*
428 **Comparative equivalent using VSR registers**
430 For a comparative data point the VSR Registers may be expressed in the
431 same fashion. The c code below is directly an expression of Figure 97 in
432 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating
433 for MSB0 numbering in both bits and elements, adapting in full to LSB0
434 numbering, and obeying LE ordering*.
436 **Crucial to understanding why the subtraction from 1,3,7,15 is present is
437 because the Power ISA numbers VSX Registers elements also in MSB0 order**.
438 SVP64 very specifically numbers elements in **LSB0** order with the first
439 element (numbered zero) being at the bitwise-numbered **LSB** end of the
440 register, where VSX does the reverse: places the numerically-*highest*
441 (last-numbered) element at the LSB end of the register.
446 // these do NOT match their Power ISA VSX numbering directly, they are all reversed
447 // bytes[15] is actually VSR.byte[0] for example. if this convention is not
448 // followed then everything ends up in the wrong place
449 uint8_t bytes[16]; // elwidth 8, QTY 16 FIXED total
450 uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total
451 uint32_t words[4]; // elwidth 32, QTY 8 FIXED total
452 uint64_t dwords[2]; // elwidth 64, QTY 2 FIXED total
453 uint8_t actual_bytes[16]; // totals 128-bit
456 elreg_t VSR_regfile[64];
458 static void check_num_elements(int elt, int width) {
460 case 64: assert elt < 2;
461 case 32: assert elt < 4;
462 case 16: assert elt < 8;
463 case 8 : assert elt < 16;
466 void get_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
467 check_num_elements(elt, width);
469 case 64: el->dwords[0] = VSR_regfile[gpr].dwords[1-elt];
470 case 32: el->words[0] = VSR_regfile[gpr].words[3-elt];
471 case 16: el->hwords[0] = VSR_regfile[gpr].hwords[7-elt];
472 case 8 : el->bytes[0] = VSR_regfile[gpr].bytes[15-elt];
475 void set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
476 check_num_elements(elt, width);
478 case 64: VSR_regfile[gpr].dwords[1-elt] = el->dwords[0];
479 case 32: VSR_regfile[gpr].words[3-elt] = el->words[0];
480 case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[0];
481 case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[0];
486 For VSR Registers one key difference is that the overlay of different
487 element widths is clearly a *bounded static quantity*, whereas for
488 Simple-V the elements are unrestrained and permitted to flow into
489 *successive underlying Scalar registers*. This difference is absolutely
490 critical to a full understanding of the entire Simple-V paradigm and
491 why element-ordering, bit-numbering *and register numbering* are all so
494 Implementations are not permitted to violate the Canonical
495 definition. Software will be critically relying on the wrapped (overflow)
496 behaviour inherently implied by the unbounded variable-length c arrays.
498 Illustrating the exact same loop with the exact same effect as achieved
499 by Simple-V we are first forced to create wrapper functions, to cater
500 for the fact that VSR register elements are static bounded:
503 int calc_VSR_reg_offs(int elt, int width) {
505 case 64: return floor(elt / 2);
506 case 32: return floor(elt / 4);
507 case 16: return floor(elt / 8);
508 case 8 : return floor(elt / 16);
511 int calc_VSR_elt_offs(int elt, int width) {
513 case 64: return (elt % 2);
514 case 32: return (elt % 4);
515 case 16: return (elt % 8);
516 case 8 : return (elt % 16);
519 void _set_VSR_element(el_reg_t* el, int gpr, int elt, int width) {
520 int new_elt = calc_VSR_elt_offs(elt, width);
521 int new_reg = calc_VSR_reg_offs(elt, width);
522 set_VSR_element(el, gpr+new_reg, new_elt, width);
526 And finally use these functions:
529 # VSX-add RT, RA, RB using the "uint64_t" union member "hwords"
531 el_reg_t result, ra, rb;
532 _get_VSR_element(&ra, RA, i, 16);
533 _get_VSR_element(&rb, RB, i, 16);
534 result.hwords[0] = ra.hwords[0] + rb.hwords[0]; // use array 0 elements
535 _set_VSR_element(&result, RT, i, 16);
539 ## Scalar Identity Behaviour
541 SVP64 is designed so that when the prefix is all zeros, and VL=1, no
542 effect or influence occurs (no augmentation) such that all standard Power
543 ISA v3.0/v3.1 instructions covered by the prefix are "unaltered". This
544 is termed `scalar identity behaviour` (based on the mathematical
545 definition for "identity", as in, "identity matrix" or better "identity
548 Note that this is completely different from when VL=0. VL=0 turns all
549 operations under its influence into `nops` (regardless of the prefix)
550 whereas when VL=1 and the SV prefix is all zeros, the operation simply
551 acts as if SV had not been applied at all to the instruction (an
552 "identity transformation").
554 The fact that `VL` is dynamic and can be set to any value at runtime
555 based on program conditions and behaviour means very specifically that
556 `scalar identity behaviour` is **not** a redundant encoding. If the only
557 means by which VL could be set was by way of static-compiled immediates
558 then this assertion would be false. VL should not be confused with
559 MAXVL when understanding this key aspect of SimpleV.
561 ## Register Naming and size
563 As indicated above SV Registers are simply the GPR, FPR and CR register
564 files extended linearly to larger sizes; SV Vectorisation iterates
565 sequentially through these registers (LSB0 sequential ordering from 0
568 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
569 r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV)
570 as r0 to r127. Likewise FP registers are
571 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
572 CR0 thru CR127. In the Lower SV Compliancy Levels the quantity of registers
573 remains the same in order to reduce implementation cost for Embedded systems.
575 The names of the registers therefore reflects a simple linear extension
576 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
577 would be reflected by a linear increase in the size of the underlying
578 SRAM used for the regfiles.
580 Note: when an EXTRA field (defined below) is zero, SV is deliberately
581 designed so that the register fields are identical to as if SV was not in
582 effect i.e. under these circumstances (EXTRA=0) the register field names
583 RA, RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.
584 This is part of `scalar identity behaviour` described above.
586 **Condition Register(s)**
588 The Scalar Power ISA Condition Register is a 64 bit register where
589 the top 32 MSBs (numbered 0:31 in MSB0 numbering) are not used.
590 This convention is *preserved* in SVP64 and an additional 15 Condition
591 Registers provided in order to store the new CR Fields, CR8-CR15,
592 CR16-CR23 etc. sequentially. The top 32 MSBs in each new SVP64 Condition
593 Register are *also* not used: only the bottom 32 bits (numbered 32:63
596 *Programmer's note: using `sv.mfcr` without element-width overrides
597 to take into account the fact that the top 32 MSBs are zero and thus
598 effectively doubling the number of GPR registers required to hold all 128
599 CR Fields would seem the only option because a source elwidth override
600 to 32-bit would take only the bottom 16 LSBs of the Condition Register
601 and set the top 16 LSBs to zeros. However in this case it
602 is possible to use destination element-width overrides (for `sv.mfcr`.
603 source overrides would be used on the GPR of `sv.mtocrf`), whereupon
604 truncation of the 64-bit Condition Register(s) occurs, throwing away
605 the zeros and storing the remaining (valid, desired) 32-bit values
606 sequentially into (LSB0-convention) lower-numbered and upper-numbered
607 halves of GPRs respectively. The programmer is expected to be aware
608 however that the full width of the entire 64-bit Condition Register
609 is considered to be "an element". This is **not** like any other
610 Condition-Register instructions because all other CR instructions,
611 on closer investigation, will be observed to all be CR-bit or CR-Field
612 related. Thus a `VL` of 16 must be used*
614 **Condition Register Fields as Predicate Masks**
616 Condition Register Fields perform an additional duty in Simple-V: they are
617 used for Predicate Masks. ARM's Scalar Instruction Set calls single-bit
618 predication "Conditional Execution", and utilises Condition Codes for
619 exactly this purpose to solve the problem caused by Branch Speculation.
620 In a Vector ISA context the concept of Predication is naturally extended
621 from single-bit to multi-bit, and the (well-known) benefits become all the
622 more critical given that parallel branches in Vector ISAs are impossible
623 (even a Vector ISA can only have Scalar branches).
625 However the Scalar Power ISA does not have Conditional Execution (for
626 which, if it had ever been considered, Condition Register bits would be
627 a perfect natural fit). Thus, when adding Predication using CR Fields
628 via Simple-V it becomes a somewhat disruptive addition to the Power ISA.
630 To ameliorate this situation, particularly for pre-existing Hardware
631 designs implementing up to Scalar Power ISA v3.1, some rules are set that
632 allow those pre-existing designs not to require heavy modification to
633 their existing Scalar pipelines. These rules effectively allow Hardware
634 Architects to add the additional CR Fields CR8 to CR127 as if they were
635 an **entirely separate register file**.
637 * any instruction involving more than 1 source 1 destination
638 where one of the operands is a Condition Register is prohibited from
639 using registers from both the CR0-7 group and the CR8-127 group at
641 * any instruction involving 1 source 1 destination where either the
642 source or the destination is a Condition Register is prohibited
643 from setting CR0-7 as a Vector.
644 * prohibitions are required to be enforced by raising Illegal Instruction
647 Examples of permitted instructions:
650 sv.crand *cr8.eq, *cr16.le, *cr40.so # all CR8-CR127
651 sv.mfcr cr5, *cr40 # only one source (CR40) copied to CR5
652 sv.mfcr *cr16, cr40 # Vector-Splat CR40 onto CR16,17,18...
653 sv.mfcr *cr16, cr3 # Vector-Splat CR3 onto CR16,17,18...
656 Examples of prohibited instructions:
659 sv.mfcr *cr0, cr40 # Vector-Splat onto CR0,1,2
660 sv.crand cr7, cr9, cr10 # crosses over between CR0-7 and CR8-127
665 With the way that EXTRA fields are defined and applied to register
666 fields, future versions of SV may involve 256 or greater registers
667 in some way as long as the reputation of Power ISA for full backwards
668 binary interoperability is preserved. Backwards binary compatibility
669 may be achieved with a PCR bit (Program Compatibility Register) or an
670 MSR bit analogous to SF. Further discussion is out of scope for this
673 Additionally, a future variant of SVP64 will be applied to the Scalar
674 (Quad-precision and 128-bit) VSX instructions. Element-width overrides are
675 an opportunity to expand a future version of the Power ISA to 256-bit,
676 512-bit and 1024-bit operations, as well as doubling or quadrupling the
677 number of VSX registers to 128 or 256. Again further discussion is out
678 of scope for this version of SVP64.
684 ## SVP64 Remapped Encoding (`RM[0:23]`)
686 In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits
687 32-37 are the Primary Opcode of the Suffix "Defined Word". 38-63 are the
688 remainder of the Defined Word. Note that the new EXT232-263 SVP64 area
689 it is obviously mandatory that bit 32 is required to be set to 1.
691 | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description |
692 |-----|---|---|----------|--------|----------|-----------------------|
693 | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 |
694 | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 |
696 It is important to note that unlike EXT1xx 64-bit prefixed instructions
697 there is insufficient space in `RM` to provide identification of
698 any SVP64 Fields without first partially decoding the 32-bit suffix.
699 Similar to the "Forms" (X-Form, D-Form) the `RM` format is individually
700 associated with every instruction. However this still does not adversely
701 affect Multi-Issue Decoding because the identification of the *length*
702 of anything in the 64-bit space has been kept brutally simple (EXT009),
703 and further decoding of any number of 64-bit Encodings in parallel at
704 that point is fully independent.
706 Extreme caution and care must be taken when extending SVP64
707 in future, to not create unnecessary relationships between prefix and
708 suffix that could complicate decoding, adding latency.
712 The following fields are common to all Remapped Encodings:
714 | Field Name | Field bits | Description |
715 |------------|------------|----------------------------------------|
716 | MASKMODE | `0` | Execution (predication) Mask Kind |
717 | MASK | `1:3` | Execution Mask |
718 | SUBVL | `8:9` | Sub-vector length |
720 The following fields are optional or encoded differently depending
721 on context after decoding of the Scalar suffix:
723 | Field Name | Field bits | Description |
724 |------------|------------|----------------------------------------|
725 | ELWIDTH | `4:5` | Element Width |
726 | ELWIDTH_SRC | `6:7` | Element Width for Source |
727 | EXTRA | `10:18` | Register Extra encoding |
728 | MODE | `19:23` | changes Vector behaviour |
730 * MODE changes the behaviour of the SV operation (result saturation,
732 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D
733 and Audio/Video DSP work
734 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and
736 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of
737 sources: scalar INT and Vector CR).
738 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category
739 for the instruction, which is determined only by decoding the Scalar 32
742 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations,
743 such as `RM-1P-3S1D` which indicates for this example that the operation
744 is to be single-predicated and that there are 3 source operand EXTRA
745 tags and one destination operand tag.
747 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
748 or increased latency in some implementations due to lane-crossing.
752 Mode is an augmentation of SV behaviour. Different types of instructions
753 have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
754 formats apply to different instruction types. Modes include Reduction,
755 Iteration, arithmetic saturation, and Fail-First. More specific details
756 in each section and in the [[svp64/appendix]]
758 * For condition register operations see [[sv/cr_ops]]
759 * For LD/ST Modes, see [[sv/ldst]].
760 * For Branch modes, see [[sv/branches]]
761 * For arithmetic and logical, see [[sv/normal]]
765 Default behaviour is set to 0b00 so that zeros follow the convention
766 of `scalar identity behaviour`. In this case it means that elwidth
767 overrides are not applicable. Thus if a 32 bit instruction operates
768 on 32 bit, `elwidth=0b00` specifies that this behaviour is unmodified.
769 Likewise when a processor is switched from 64 bit to 32 bit mode,
770 `elwidth=0b00` states that, again, the behaviour is not to be modified.
772 Only when elwidth is nonzero is the element width overridden to the
773 explicitly required value.
775 ### Elwidth for Integers:
777 | Value | Mnemonic | Description |
778 |-------|----------------|------------------------------------|
779 | 00 | DEFAULT | default behaviour for operation |
780 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
781 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
782 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
784 This encoding is chosen such that the byte width may be computed as
787 ### Elwidth for FP Registers:
789 | Value | Mnemonic | Description |
790 |-------|----------------|------------------------------------|
791 | 00 | DEFAULT | default behaviour for FP operation |
792 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
793 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
794 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
797 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
798 is reserved for a future implementation of SV
800 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`)
801 shall perform its operation at **half** the ELWIDTH then padded back out
802 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation
803 that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
804 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
805 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
806 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16 or
807 ELWIDTH=bf16 is reserved and must raise an illegal instruction (IEEE754
808 FP8 or BF8 are not defined).
810 ### Elwidth for CRs (no meaning)
812 Element-width overrides for CR Fields has no meaning. The bits
813 are therefore used for other purposes, or when Rc=1, the Elwidth
814 applies to the result being tested (a GPR or FPR), but not to the
819 The default for SUBVL is 1 and its encoding is 0b00 to indicate that
820 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
821 lines up in combination with all other "default is all zeros" behaviour.
823 | Value | Mnemonic | Subvec | Description |
824 |-------|-----------|---------|------------------------|
825 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
826 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
827 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
828 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
830 The SUBVL encoding value may be thought of as an inclusive range of a
831 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
832 this may be considered to be elements 0b00 to 0b01 inclusive.
834 Effectively, SUBVL is like a SIMD multiplier: instead of just 1
835 element operation issued, SUBVL element operations are issued (as an inner loop).
836 The key difference between VL looping and SUBVL looping
837 is that predication bits are applied per
838 **group**, rather than by individual element.
840 Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
842 ## MASK/MASK_SRC & MASKMODE Encoding
844 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
845 types may not be mixed.
847 Special note: to disable predication this field must be set to zero in
848 combination with Integer Predication also being set to 0b000. this has the
849 effect of enabling "all 1s" in the predicate mask, which is equivalent to
850 "not having any predication at all".
852 `MASKMODE` may be set to one of 2 values:
854 | Value | Description |
855 |-----------|------------------------------------------------------|
856 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
857 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
859 Integer Twin predication has a second set of 3 bits that uses the same
860 encoding thus allowing either the same register (r3, r10 or r31) to be
861 used for both src and dest, or different regs (one for src, one for dest).
863 Likewise CR based twin predication has a second set of 3 bits, allowing
864 a different test to be applied.
866 Note that it cannot necessarily be assumed that Predicate Masks
867 (whether INT or CR) are read in full *before* the operations proceed. In practice (for CR Fields)
868 this creates an unnecessary block on parallelism, prohibiting
869 "Vector Chaining". Therefore, it is up
870 to the programmer to ensure that the CR field Elements used as Predicate Masks
871 are not overwritten by any parallel Vector Loop. Doing so results
872 in **UNDEFINED** behaviour, according to the definition outlined in the
873 Power ISA v3.0B Specification.
875 Hardware Implementations are therefore free and clear to delay reading
876 of individual CR fields until the actual predicated element operation
877 needs to take place, safe in the knowledge that no programmer will have
878 issued a Vector Instruction where previous elements could have overwritten
879 (destroyed) not-yet-executed CR-Predicated element operations.
880 This particularly is an issue when using REMAP, as the order in
881 which CR-Field-based Predicate Mask bits could be read on a per-element
882 execution basis could well conflict with the order in which prior
883 elements wrote to the very same CR Field.
885 Additionally Programmers should avoid using r3 r10 or r30
886 as destination registers when these are also used as a Predicate
887 Mask. Doing so is again UNDEFINED behaviour.
889 ### Integer Predication (MASKMODE=0)
891 When the predicate mode bit is zero the 3 bits are interpreted as below.
892 Twin predication has an identical 3 bit field similarly encoded.
894 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
897 | Value | Mnemonic | Element `i` enabled if: |
898 |-------|----------|------------------------------|
899 | 000 | ALWAYS | predicate effectively all 1s |
900 | 001 | 1 << R3 | `i == R3` |
901 | 010 | R3 | `R3 & (1 << i)` is non-zero |
902 | 011 | ~R3 | `R3 & (1 << i)` is zero |
903 | 100 | R10 | `R10 & (1 << i)` is non-zero |
904 | 101 | ~R10 | `R10 & (1 << i)` is zero |
905 | 110 | R30 | `R30 & (1 << i)` is non-zero |
906 | 111 | ~R30 | `R30 & (1 << i)` is zero |
908 r10 and r30 are at the high end of temporary and unused registers,
909 so as not to interfere with register allocation from ABIs.
912 ### CR-based Predication (MASKMODE=1)
914 When the predicate mode bit is one the 3 bits are interpreted as below.
915 Twin predication has an identical 3 bit field similarly encoded.
917 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the
920 | Value | Mnemonic | Element `i` is enabled if |
921 |-------|----------|--------------------------|
922 | 000 | lt | `CR[offs+i].LT` is set |
923 | 001 | nl/ge | `CR[offs+i].LT` is clear |
924 | 010 | gt | `CR[offs+i].GT` is set |
925 | 011 | ng/le | `CR[offs+i].GT` is clear |
926 | 100 | eq | `CR[offs+i].EQ` is set |
927 | 101 | ne | `CR[offs+i].EQ` is clear |
928 | 110 | so/un | `CR[offs+i].FU` is set |
929 | 111 | ns/nu | `CR[offs+i].FU` is clear |
931 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised
932 Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
934 The CR Predicates chosen must start on a boundary that Vectorised CR
935 operations can access cleanly, in full. With EXTRA2 restricting starting
936 points to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and
937 CR Predicate Masks have to be adapted to fit on these boundaries as well.
939 ## Extra Remapped Encoding <a name="extra_remap"> </a>
941 Shows all instruction-specific fields in the Remapped Encoding
942 `RM[10:18]` for all instruction variants. Note that due to the very
943 tight space, the encoding mode is *not* included in the prefix itself.
944 The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form)
945 on a per-instruction basis, and, like "Forms" are given a designation
946 (below) of the form `RM-nP-nSnD`. The full list of which instructions
947 use which remaps is here [[opcode_regs_deduped]].
949 **Please note the following**:
952 Machine-readable CSV files have been autogenerated which will make the
953 task of creating SV-aware ISA decoders, documentation, assembler tools
954 compiler tools Simulators documentation all aspects of SVP64 easier
955 and less prone to mistakes. Please avoid manual re-creation of
956 information from the written specification wording in this chapter,
957 and use the CSV files or use the Canonical tool which creates the CSV
958 files, named sv_analysis.py. The information contained within
959 sv_analysis.py is considered to be part of this Specification, even
960 encoded as it is in python3.
964 The mappings are part of the SVP64 Specification in exactly the same
965 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
966 will need a corresponding SVP64 Mapping, which can be derived by-rote
967 from examining the Register "Profile" of the instruction.
969 There are two categories: Single and Twin Predication. Due to space
970 considerations further subdivision of Single Predication is based on
971 whether the number of src operands is 2 or 3. With only 9 bits available
972 some compromises have to be made.
974 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand
975 instructions (fmadd, isel, madd).
976 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand
977 instructions (src1 src2 dest)
978 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
979 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
980 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
984 | Field Name | Field bits | Description |
985 |------------|------------|----------------------------------------|
986 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
987 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
988 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
989 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
990 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
992 These are for 3 operand in and either 1 or 2 out instructions.
993 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
994 such as `maddedu` have an implicit second destination, RS, the
995 selection of which is determined by bit 18.
999 | Field Name | Field bits | Description |
1000 |------------|------------|-------------------------------------------|
1001 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
1002 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
1003 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
1005 These are for 2 operand 1 dest instructions, such as `add RT, RA,
1006 RB`. However also included are unusual instructions with an implicit
1007 dest that is identical to its src reg, such as `rlwinmi`.
1009 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would
1010 not have sufficient bit fields to allow an alternative destination.
1011 With SV however this becomes possible. Therefore, the fact that the
1012 dest is implicitly also a src should not mislead: due to the *prefix*
1013 they are different SV regs.
1015 * `rlwimi RA, RS, ...`
1016 * Rsrc1_EXTRA3 applies to RS as the first src
1017 * Rsrc2_EXTRA3 applies to RA as the second src
1018 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
1020 With the addition of the EXTRA bits, the three registers
1021 each may be *independently* made vector or scalar, and be independently
1022 augmented to 7 bits in length.
1026 | Field Name | Field bits | Description |
1027 |------------|------------|----------------------------|
1028 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1029 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1030 | MASK_SRC | `16:18` | Execution Mask for Source |
1032 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
1034 | Field Name | Field bits | Description |
1035 |------------|------------|----------------------------|
1036 | Rsrc1_EXTRA3 | `10:12` | extends Rsrc1 |
1037 | Rsrc2_EXTRA3 | `13:15` | extends Rsrc2 |
1038 | MASK_SRC | `16:18` | Execution Mask for Source |
1042 single-predicate, three registers (2 read, 1 write)
1044 | Field Name | Field bits | Description |
1045 |------------|------------|----------------------------|
1046 | Rdest_EXTRA3 | `10:12` | extends Rdest |
1047 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
1048 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
1050 ### RM-2P-2S1D/1S2D/3S
1052 The primary purpose for this encoding is for Twin Predication on LOAD
1053 and STORE operations. see [[sv/ldst]] for detailed analysis.
1057 | Field Name | Field bits | Description |
1058 |------------|------------|----------------------------|
1059 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1060 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1061 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1062 | MASK_SRC | `16:18` | Execution Mask for Source |
1066 For RM-2P-1S2D dest2 is in bits 14:15
1068 | Field Name | Field bits | Description |
1069 |------------|------------|----------------------------|
1070 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
1071 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1072 | Rdest2_EXTRA2 | `14:15` | extends Rdest22 (R\*\_EXTRA2 Encoding) |
1073 | MASK_SRC | `16:18` | Execution Mask for Source |
1077 Also that for RM-2P-3S (to cover `stdx` etc.) the names are switched to 3 src:
1078 Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
1080 | Field Name | Field bits | Description |
1081 |------------|------------|----------------------------|
1082 | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
1083 | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
1084 | Rsrc3_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
1085 | MASK_SRC | `16:18` | Execution Mask for Source |
1087 Note also that LD with update indexed, which takes 2 src and
1088 creates 2 dest registers (e.g. `lhaux RT,RA,RB`), does not have room
1089 for 4 registers and also Twin Predication. Therefore these are treated as
1090 RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest.
1092 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
1093 or increased latency in some implementations due to lane-crossing.
1097 EXTRA is the means by which two things are achieved:
1099 1. Registers are marked as either Vector *or Scalar*
1100 2. Register field numbers (limited typically to 5 bit)
1101 are extended in range, both for Scalar and Vector.
1103 The register files are therefore extended:
1105 * INT (GPR) is extended from r0-31 to r0-127
1106 * FP (FPR) is extended from fp0-32 to fp0-fp127
1107 * CR Fields are extended from CR0-7 to CR0-127
1109 However due to pressure in `RM.EXTRA` not all these registers
1110 are accessible by all instructions, particularly those with
1111 a large number of operands (`madd`, `isel`).
1113 In the following tables register numbers are constructed from the
1114 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2 or
1115 EXTRA3 field from the SV Prefix, determined by the specific RM-xx-yyyy
1116 designation for a given instruction. The prefixing is arranged so that
1117 interoperability between prefixing and nonprefixing of scalar registers
1118 is direct and convenient (when the EXTRA field is all zeros).
1120 A pseudocode algorithm explains the relationship, for INT/FP (see
1121 [[svp64/appendix]] for CRs)
1127 spec = EXTRA2 << 1 # same as EXTRA3, shifted
1128 if spec[0]: # vector
1129 return (RA << 2) | spec[1:2]
1131 return (spec[1:2] << 5) | RA
1134 Future versions may extend to 256 by shifting Vector numbering up.
1135 Scalar will not be altered.
1137 Note that in some cases the range of starting points for Vectors
1142 If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
1145 Fields are as follows:
1148 * Mode: register is tagged as scalar or vector
1149 * Range/Inc: the range of registers accessible from this EXTRA
1150 encoding, and the "increment" (accessibility). "/4" means
1151 that this EXTRA encoding may only give access (starting point)
1153 * MSB..LSB: the bit field showing how the register opcode field
1154 combines with EXTRA to give (extend) the register number (GPR)
1156 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1158 | Value | Mode | Range/Inc | 6..0 |
1159 |-----------|-------|---------------|---------------------|
1160 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
1161 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
1162 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
1163 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
1164 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
1165 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
1166 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
1167 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
1171 If EXTRA2 is zero will map to "scalar identity behaviour" i.e Scalar
1172 Power ISA register naming:
1174 Encoding shown in LSB0: MSB down to LSB (MSB 6..0 LSB)
1176 | Value | Mode | Range/inc | 6..0 |
1177 |----------|-------|---------------|-----------|
1178 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
1179 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
1180 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
1181 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
1183 **Note that unlike in EXTRA3, in EXTRA2**:
1185 * the GPR Vectors may only start from
1186 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
1187 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
1189 as there is insufficient bits to cover the full range.
1193 CR Field encoding is essentially the same but made more complex due to CRs
1194 being bit-based, because the application of SVP64 element-numbering applies
1195 to the CR *Field* numbering not the CR register *bit* numbering.
1196 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
1197 and Scalars may only go from `CR0, CR1, ... CR31`
1199 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1200 BA ranges are in MSB0.
1202 For a 5-bit operand (BA, BB, BT):
1204 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1205 |-------|------|---------------|-----------| --------|---------|
1206 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1207 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1208 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[0:2] | BA[3:4] |
1209 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[0:2] | BA[3:4] |
1210 | 100 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1211 | 101 | Vector | `CR4-CR116`/16 | BA[0:2] 0 | 0b100 | BA[3:4] |
1212 | 110 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1213 | 111 | Vector | `CR12-CR124`/16 | BA[0:2] 1 | 0b100 | BA[3:4] |
1215 For a 3-bit operand (e.g. BFA):
1217 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1218 |-------|------|---------------|-----------| --------|
1219 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1220 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1221 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
1222 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
1223 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1224 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
1225 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1226 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
1230 CR encoding is essentially the same but made more complex due to CRs
1231 being bit-based, because the application of SVP64 element-numbering applies
1232 to the CR *Field* numbering not the CR register *bit* numbering.
1233 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
1235 Encoding shown in LSB0: MSB down to LSB (MSB 8..5 4..2 1..0 LSB),
1236 BA ranges are in MSB0.
1238 For a 5-bit operand (BA, BB, BC):
1240 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
1241 |-------|--------|----------------|---------|---------|---------|
1242 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[0:2] | BA[3:4] |
1243 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[0:2] | BA[3:4] |
1244 | 10 | Vector | `CR0-CR112`/16 | BA[0:2] 0 | 0b000 | BA[3:4] |
1245 | 11 | Vector | `CR8-CR120`/16 | BA[0:2] 1 | 0b000 | BA[3:4] |
1247 For a 3-bit operand (e.g. BFA):
1249 | Value | Mode | Range/Inc | 6..3 | 2..0 |
1250 |-------|------|---------------|-----------| --------|
1251 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
1252 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
1253 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
1254 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
1259 Now at its own page: [[svp64/appendix]]