(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 63f23149ad84722c42f30f770c59af4cc047a8b2..cae386c2d03b39c5c7568af44908630bf12a7191 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -77,10 +77,10 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
 |6 | 7 |19:20|21 | 22:23   |  description     |
 |--|---|-----|---|---------|------------------|
-|/ | / |0 RG | 0 | dz  sz  | simple mode                      |
-|/ | / |0 RG | 1 | dz  sz  | scalar reduce mode (mapreduce) |
-|zz|SNZ|1 VLI|inv|  CR-bit | Ffirst 3-bit mode      |
-|/ |SNZ|1 VLI|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |
+|/ | / |RG 0 | 0 | dz  sz  | simple mode                      |
+|/ | / |RG 0 | 1 | dz  sz  | scalar reduce mode (mapreduce) |
+|zz|SNZ|VLI 1|inv|  CR-bit | Ffirst 3-bit mode      |
+|/ |SNZ|VLI 1|inv|  dz sz  | Ffirst 5-bit mode (implies CR-bit from result) |
 
 Fields:
 
@@ -92,8 +92,8 @@ Fields:
   SNZ=1 a value "1" is put in place of "0".
 * **inv CR-bit** just as in branches (BO) these bits allow testing of
   a CR bit and whether it is set (inv=0) or unset (inv=1)
-* **RG** inverts the Vector Loop order (VL-1 downto 0) rather
-  than the normal 0..VL-1
+* **RG** Reverse-Gear: inverts the Vector Loop order (VL-1 downto 0) rather
+  than the normal 0 upto VL-1
 * **SVM** sets "subvector" reduce mode
 * **VLi** VL inclusive: in fail-first mode, the truncation of
   VL *includes* the current element at the failure point rather