3 #include "debug_module.h"
4 #include "debug_defines.h"
8 #include "debug_rom/debug_rom.h"
16 ///////////////////////// debug_module_data_t
18 debug_module_data_t::debug_module_data_t()
20 memset(data
, 0, sizeof(data
));
23 bool debug_module_data_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
25 D(fprintf(stderr
, "debug_module_data_t load 0x%lx bytes at 0x%lx\n", len
,
28 if (addr
+ len
< sizeof(data
)) {
29 memcpy(bytes
, data
+ addr
, len
);
33 fprintf(stderr
, "ERROR: invalid load from debug_module_data_t: %zd bytes at 0x%016"
34 PRIx64
"\n", len
, addr
);
39 bool debug_module_data_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
41 D(fprintf(stderr
, "debug_module_data_t store 0x%lx bytes at 0x%lx\n", len
,
44 if (addr
+ len
< sizeof(data
)) {
45 memcpy(data
+ addr
, bytes
, len
);
49 fprintf(stderr
, "ERROR: invalid store to debug_module_data_t: %zd bytes at 0x%016"
50 PRIx64
"\n", len
, addr
);
54 uint32_t debug_module_data_t::read32(reg_t addr
) const
56 assert(addr
+ 4 <= sizeof(data
));
58 (data
[addr
+ 1] << 8) |
59 (data
[addr
+ 2] << 16) |
60 (data
[addr
+ 3] << 24);
63 void debug_module_data_t::write32(reg_t addr
, uint32_t value
)
65 fprintf(stderr
, "debug_module_data_t::write32(0x%lx, 0x%x)\n", addr
, value
);
66 assert(addr
+ 4 <= sizeof(data
));
67 data
[addr
] = value
& 0xff;
68 data
[addr
+ 1] = (value
>> 8) & 0xff;
69 data
[addr
+ 2] = (value
>> 16) & 0xff;
70 data
[addr
+ 3] = (value
>> 24) & 0xff;
73 ///////////////////////// debug_module_t
75 debug_module_t::debug_module_t(sim_t
*sim
) : sim(sim
),
76 next_action(jal(ZERO
, 0)),
77 action_executed(false)
80 dmcontrol
.version
= 1;
82 for (unsigned i
= 0; i
< DEBUG_ROM_ENTRY_SIZE
/ 4; i
++) {
83 write32(debug_rom_entry
, i
, jal(ZERO
, 0));
87 memset(program_buffer
, 0, sizeof(program_buffer
));
90 void debug_module_t::reset()
92 for (unsigned i
= 0; i
< sim
->nprocs(); i
++) {
93 processor_t
*proc
= sim
->get_core(i
);
95 proc
->halt_request
= false;
99 dmcontrol
.authenticated
= 1;
100 dmcontrol
.version
= 1;
101 dmcontrol
.authtype
= dmcontrol
.AUTHTYPE_NOAUTH
;
104 abstractcs
.datacount
= sizeof(dmdata
.data
) / 4;
107 void debug_module_t::add_device(bus_t
*bus
) {
108 bus
->add_device(DEBUG_START
, this);
109 bus
->add_device(DEBUG_EXCHANGE
, &dmdata
);
112 bool debug_module_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
114 D(fprintf(stderr
, "debug_module_t load 0x%lx bytes at 0x%lx\n",
116 addr
= DEBUG_START
+ addr
;
118 if (addr
>= DEBUG_ROM_ENTRY
&&
119 addr
< DEBUG_ROM_ENTRY
+ DEBUG_ROM_ENTRY_SIZE
) {
121 if (read32(debug_rom_entry
, dmcontrol
.hartsel
) == jal(ZERO
, 0)) {
122 // We're here in an infinite loop. That means that whatever abstract
123 // command has complete.
124 abstractcs
.busy
= false;
127 action_executed
= true;
129 halted
[(addr
- DEBUG_ROM_ENTRY
) / 4] = true;
130 memcpy(bytes
, debug_rom_entry
+ addr
- DEBUG_ROM_ENTRY
, len
);
134 if (action_executed
) {
135 // Restore the jump-to-self loop.
136 write32(debug_rom_entry
, dmcontrol
.hartsel
, next_action
);
137 next_action
= jal(ZERO
, 0);
138 action_executed
= false;
141 if (addr
>= DEBUG_ROM_CODE
&&
142 addr
< DEBUG_ROM_CODE
+ DEBUG_ROM_CODE_SIZE
) {
144 if (read32(debug_rom_code
, 0) == dret()) {
145 abstractcs
.busy
= false;
146 halted
[dmcontrol
.hartsel
] = false;
149 memcpy(bytes
, debug_rom_code
+ addr
- DEBUG_ROM_CODE
, len
);
153 if (addr
>= DEBUG_RAM_START
&& addr
< DEBUG_RAM_END
) {
154 memcpy(bytes
, program_buffer
+ addr
- DEBUG_RAM_START
, len
);
158 if (addr
>= DEBUG_ROM_EXCEPTION
&&
159 addr
< DEBUG_ROM_EXCEPTION
+ DEBUG_ROM_EXCEPTION_SIZE
) {
160 memcpy(bytes
, debug_rom_exception
+ addr
- DEBUG_ROM_EXCEPTION
, len
);
161 if (abstractcs
.cmderr
== abstractcs
.CMDERR_NONE
) {
162 abstractcs
.cmderr
= abstractcs
.CMDERR_EXCEPTION
;
167 fprintf(stderr
, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
168 PRIx64
"\n", len
, addr
);
173 bool debug_module_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
175 addr
= DEBUG_START
+ addr
;
177 if (addr
>= DEBUG_RAM_START
&& addr
< DEBUG_RAM_END
) {
178 memcpy(program_buffer
+ addr
- DEBUG_RAM_START
, bytes
, len
);
182 fprintf(stderr
, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
183 PRIx64
"\n", len
, addr
);
187 void debug_module_t::write32(uint8_t *memory
, unsigned int index
, uint32_t value
)
189 uint8_t* base
= memory
+ index
* 4;
190 base
[0] = value
& 0xff;
191 base
[1] = (value
>> 8) & 0xff;
192 base
[2] = (value
>> 16) & 0xff;
193 base
[3] = (value
>> 24) & 0xff;
196 uint32_t debug_module_t::read32(uint8_t *memory
, unsigned int index
)
198 uint8_t* base
= memory
+ index
* 4;
199 uint32_t value
= ((uint32_t) base
[0]) |
200 (((uint32_t) base
[1]) << 8) |
201 (((uint32_t) base
[2]) << 16) |
202 (((uint32_t) base
[3]) << 24);
206 processor_t
*debug_module_t::current_proc() const
208 processor_t
*proc
= NULL
;
210 proc
= sim
->get_core(dmcontrol
.hartsel
);
211 } catch (const std::out_of_range
&) {
216 bool debug_module_t::dmi_read(unsigned address
, uint32_t *value
)
219 D(fprintf(stderr
, "dmi_read(0x%x) -> ", address
));
220 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
221 result
= dmdata
.read32(4 * (address
- DMI_DATA0
));
222 } else if (address
>= DMI_IBUF0
&& address
< DMI_IBUF0
+ progsize
) {
223 result
= read32(program_buffer
, address
- DMI_IBUF0
);
228 processor_t
*proc
= current_proc();
230 if (halted
[dmcontrol
.hartsel
]) {
231 dmcontrol
.hartstatus
= dmcontrol
.HARTSTATUS_HALTED
;
233 dmcontrol
.hartstatus
= dmcontrol
.HARTSTATUS_RUNNING
;
235 dmcontrol
.haltreq
= proc
->halt_request
;
237 dmcontrol
.hartstatus
= dmcontrol
.HARTSTATUS_NOTEXIST
;
239 result
= set_field(result
, DMI_DMCONTROL_HALTREQ
, dmcontrol
.haltreq
);
240 result
= set_field(result
, DMI_DMCONTROL_RESET
, dmcontrol
.reset
);
241 result
= set_field(result
, DMI_DMCONTROL_DMACTIVE
, dmcontrol
.dmactive
);
242 result
= set_field(result
, DMI_DMCONTROL_HARTSTATUS
, dmcontrol
.hartstatus
);
243 result
= set_field(result
, DMI_DMCONTROL_HARTSEL
, dmcontrol
.hartsel
);
244 result
= set_field(result
, DMI_DMCONTROL_AUTHENTICATED
, dmcontrol
.authenticated
);
245 result
= set_field(result
, DMI_DMCONTROL_AUTHBUSY
, dmcontrol
.authbusy
);
246 result
= set_field(result
, DMI_DMCONTROL_AUTHTYPE
, dmcontrol
.authtype
);
247 result
= set_field(result
, DMI_DMCONTROL_VERSION
, dmcontrol
.version
);
251 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC7
, abstractcs
.autoexec7
);
252 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC6
, abstractcs
.autoexec6
);
253 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC5
, abstractcs
.autoexec5
);
254 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC4
, abstractcs
.autoexec4
);
255 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC3
, abstractcs
.autoexec3
);
256 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC2
, abstractcs
.autoexec2
);
257 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC1
, abstractcs
.autoexec1
);
258 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC0
, abstractcs
.autoexec0
);
259 result
= set_field(result
, DMI_ABSTRACTCS_CMDERR
, abstractcs
.cmderr
);
260 result
= set_field(result
, DMI_ABSTRACTCS_BUSY
, abstractcs
.busy
);
261 result
= set_field(result
, DMI_ABSTRACTCS_DATACOUNT
, abstractcs
.datacount
);
264 result
= progsize
<< DMI_ACCESSCS_PROGSIZE_OFFSET
;
270 D(fprintf(stderr
, "error\n"));
274 D(fprintf(stderr
, "0x%x\n", result
));
279 bool debug_module_t::perform_abstract_command(uint32_t command
)
281 if (abstractcs
.cmderr
!= abstractcs
.CMDERR_NONE
)
283 if (abstractcs
.busy
) {
284 abstractcs
.cmderr
= abstractcs
.CMDERR_BUSY
;
288 if ((command
>> 24) == 0) {
290 unsigned size
= get_field(command
, AC_ACCESS_REGISTER_SIZE
);
291 bool write
= get_field(command
, AC_ACCESS_REGISTER_WRITE
);
292 unsigned regno
= get_field(command
, AC_ACCESS_REGISTER_REGNO
);
294 if (regno
< 0x1000 || regno
>= 0x1020) {
295 abstractcs
.cmderr
= abstractcs
.CMDERR_NOTSUP
;
299 unsigned regnum
= regno
- 0x1000;
301 if (!halted
[dmcontrol
.hartsel
]) {
302 abstractcs
.cmderr
= abstractcs
.CMDERR_HALTRESUME
;
309 write32(debug_rom_code
, 0, lw(regnum
, ZERO
, DEBUG_EXCHANGE
));
311 write32(debug_rom_code
, 0, sw(regnum
, ZERO
, DEBUG_EXCHANGE
));
315 write32(debug_rom_code
, 0, ld(regnum
, ZERO
, DEBUG_EXCHANGE
));
317 write32(debug_rom_code
, 0, sd(regnum
, ZERO
, DEBUG_EXCHANGE
));
322 write32(debug_rom_code, 0, lq(regnum, ZERO, DEBUG_EXCHANGE));
324 write32(debug_rom_code, 0, sq(regnum, ZERO, DEBUG_EXCHANGE));
328 abstractcs
.cmderr
= abstractcs
.CMDERR_NOTSUP
;
331 if (get_field(command
, AC_ACCESS_REGISTER_POSTEXEC
)) {
332 write32(debug_rom_code
, 1, jal(ZERO
, DEBUG_RAM_START
- DEBUG_ROM_CODE
- 4));
334 write32(debug_rom_code
, 1, ebreak());
337 if (get_field(command
, AC_ACCESS_REGISTER_PREEXEC
)) {
338 write32(debug_rom_entry
, dmcontrol
.hartsel
,
339 jal(ZERO
, DEBUG_RAM_START
- (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
)));
341 jal(ZERO
, DEBUG_ROM_CODE
- (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
));
343 write32(debug_rom_entry
, dmcontrol
.hartsel
,
344 jal(ZERO
, DEBUG_ROM_CODE
- (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
)));
347 write32(debug_rom_exception
, dmcontrol
.hartsel
,
348 jal(ZERO
, (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
) - DEBUG_ROM_EXCEPTION
));
349 abstractcs
.busy
= true;
351 abstractcs
.cmderr
= abstractcs
.CMDERR_NOTSUP
;
356 bool debug_module_t::dmi_write(unsigned address
, uint32_t value
)
358 D(fprintf(stderr
, "dmi_write(0x%x, 0x%x)\n", address
, value
));
359 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
360 dmdata
.write32(4 * (address
- DMI_DATA0
), value
);
362 } else if (address
>= DMI_IBUF0
&& address
< DMI_IBUF0
+ progsize
) {
363 write32(program_buffer
, address
- DMI_IBUF0
, value
);
369 dmcontrol
.dmactive
= get_field(value
, DMI_DMCONTROL_DMACTIVE
);
370 if (dmcontrol
.dmactive
) {
371 dmcontrol
.haltreq
= get_field(value
, DMI_DMCONTROL_HALTREQ
);
372 dmcontrol
.resumereq
= get_field(value
, DMI_DMCONTROL_RESUMEREQ
);
373 dmcontrol
.reset
= get_field(value
, DMI_DMCONTROL_RESET
);
374 dmcontrol
.hartsel
= get_field(value
, DMI_DMCONTROL_HARTSEL
);
378 processor_t
*proc
= current_proc();
380 proc
->halt_request
= dmcontrol
.haltreq
;
381 if (dmcontrol
.resumereq
) {
382 write32(debug_rom_code
, 0, dret());
383 write32(debug_rom_entry
, dmcontrol
.hartsel
,
384 jal(ZERO
, DEBUG_ROM_CODE
- (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
)));
385 abstractcs
.busy
= true;
392 return perform_abstract_command(value
);
395 abstractcs
.autoexec7
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC7
);
396 abstractcs
.autoexec6
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC6
);
397 abstractcs
.autoexec5
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC5
);
398 abstractcs
.autoexec4
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC4
);
399 abstractcs
.autoexec3
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC3
);
400 abstractcs
.autoexec2
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC2
);
401 abstractcs
.autoexec1
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC1
);
402 abstractcs
.autoexec0
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC0
);
403 if (get_field(value
, DMI_ABSTRACTCS_CMDERR
) == abstractcs
.CMDERR_NONE
) {
404 abstractcs
.cmderr
= abstractcs
.CMDERR_NONE
;