3 #include "debug_module.h"
4 #include "debug_defines.h"
8 #include "debug_rom/debug_rom.h"
9 #include "debug_rom/debug_rom_defines.h"
17 ///////////////////////// debug_module_t
19 debug_module_t::debug_module_t(sim_t
*sim
, unsigned progbufsize
) :
20 progbufsize(progbufsize
),
21 program_buffer_bytes(4 + 4*progbufsize
),
22 debug_progbuf_start(debug_data_start
- program_buffer_bytes
),
23 debug_abstract_start(debug_progbuf_start
- debug_abstract_size
*4),
26 program_buffer
= new uint8_t[program_buffer_bytes
];
28 memset(halted
, 0, sizeof(halted
));
29 memset(debug_rom_flags
, 0, sizeof(debug_rom_flags
));
30 memset(resumeack
, 0, sizeof(resumeack
));
31 memset(program_buffer
, 0, program_buffer_bytes
);
32 program_buffer
[4*progbufsize
] = ebreak();
33 program_buffer
[4*progbufsize
+1] = ebreak() >> 8;
34 program_buffer
[4*progbufsize
+2] = ebreak() >> 16;
35 program_buffer
[4*progbufsize
+3] = ebreak() >> 24;
36 memset(dmdata
, 0, sizeof(dmdata
));
38 write32(debug_rom_whereto
, 0,
39 jal(ZERO
, debug_abstract_start
- DEBUG_ROM_WHERETO
));
41 memset(debug_abstract
, 0, sizeof(debug_abstract
));
46 debug_module_t::~debug_module_t()
48 delete[] program_buffer
;
51 void debug_module_t::reset()
53 for (unsigned i
= 0; i
< sim
->nprocs(); i
++) {
54 processor_t
*proc
= sim
->get_core(i
);
56 proc
->halt_request
= false;
62 dmstatus
.impebreak
= true;
63 dmstatus
.authenticated
= 1;
67 abstractcs
.datacount
= sizeof(dmdata
) / 4;
68 abstractcs
.progbufsize
= progbufsize
;
78 sbcs
.asize
= sizeof(reg_t
) * 8;
81 void debug_module_t::add_device(bus_t
*bus
) {
82 bus
->add_device(DEBUG_START
, this);
85 bool debug_module_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
87 addr
= DEBUG_START
+ addr
;
89 if (addr
>= DEBUG_ROM_ENTRY
&&
90 (addr
+ len
) <= (DEBUG_ROM_ENTRY
+ debug_rom_raw_len
)) {
91 memcpy(bytes
, debug_rom_raw
+ addr
- DEBUG_ROM_ENTRY
, len
);
95 if (addr
>= DEBUG_ROM_WHERETO
&& (addr
+ len
) <= (DEBUG_ROM_WHERETO
+ 4)) {
96 memcpy(bytes
, debug_rom_whereto
+ addr
- DEBUG_ROM_WHERETO
, len
);
100 if (addr
>= DEBUG_ROM_FLAGS
&& ((addr
+ len
) <= DEBUG_ROM_FLAGS
+ 1024)) {
101 memcpy(bytes
, debug_rom_flags
+ addr
- DEBUG_ROM_FLAGS
, len
);
105 if (addr
>= debug_abstract_start
&& ((addr
+ len
) <= (debug_abstract_start
+ sizeof(debug_abstract
)))) {
106 memcpy(bytes
, debug_abstract
+ addr
- debug_abstract_start
, len
);
110 if (addr
>= debug_data_start
&& (addr
+ len
) <= (debug_data_start
+ sizeof(dmdata
))) {
111 memcpy(bytes
, dmdata
+ addr
- debug_data_start
, len
);
115 if (addr
>= debug_progbuf_start
&& ((addr
+ len
) <= (debug_progbuf_start
+ program_buffer_bytes
))) {
116 memcpy(bytes
, program_buffer
+ addr
- debug_progbuf_start
, len
);
120 fprintf(stderr
, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
121 PRIx64
"\n", len
, addr
);
126 bool debug_module_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
131 fprintf(stderr
, "store(addr=0x%lx, len=%d, bytes=0x%08x); "
132 "hartsel=0x%x\n", addr
, (unsigned) len
, *(uint32_t *) bytes
,
136 fprintf(stderr
, "store(addr=0x%lx, len=%d, bytes=...); "
137 "hartsel=0x%x\n", addr
, (unsigned) len
, dmcontrol
.hartsel
);
145 memcpy(id_bytes
, bytes
, 4);
146 id
= read32(id_bytes
, 0);
149 addr
= DEBUG_START
+ addr
;
151 if (addr
>= debug_data_start
&& (addr
+ len
) <= (debug_data_start
+ sizeof(dmdata
))) {
152 memcpy(dmdata
+ addr
- debug_data_start
, bytes
, len
);
156 if (addr
>= debug_progbuf_start
&& ((addr
+ len
) <= (debug_progbuf_start
+ program_buffer_bytes
))) {
157 memcpy(program_buffer
+ addr
- debug_progbuf_start
, bytes
, len
);
162 if (addr
== DEBUG_ROM_HALTED
) {
165 if (dmcontrol
.hartsel
== id
) {
166 if (0 == (debug_rom_flags
[id
] & (1 << DEBUG_ROM_FLAG_GO
))){
167 if (dmcontrol
.hartsel
== id
) {
168 abstractcs
.busy
= false;
175 if (addr
== DEBUG_ROM_GOING
) {
176 debug_rom_flags
[dmcontrol
.hartsel
] &= ~(1 << DEBUG_ROM_FLAG_GO
);
180 if (addr
== DEBUG_ROM_RESUMING
) {
183 resumeack
[id
] = true;
184 debug_rom_flags
[id
] &= ~(1 << DEBUG_ROM_FLAG_RESUME
);
188 if (addr
== DEBUG_ROM_EXCEPTION
) {
189 if (abstractcs
.cmderr
== CMDERR_NONE
) {
190 abstractcs
.cmderr
= CMDERR_EXCEPTION
;
195 fprintf(stderr
, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
196 PRIx64
"\n", len
, addr
);
200 void debug_module_t::write32(uint8_t *memory
, unsigned int index
, uint32_t value
)
202 uint8_t* base
= memory
+ index
* 4;
203 base
[0] = value
& 0xff;
204 base
[1] = (value
>> 8) & 0xff;
205 base
[2] = (value
>> 16) & 0xff;
206 base
[3] = (value
>> 24) & 0xff;
209 uint32_t debug_module_t::read32(uint8_t *memory
, unsigned int index
)
211 uint8_t* base
= memory
+ index
* 4;
212 uint32_t value
= ((uint32_t) base
[0]) |
213 (((uint32_t) base
[1]) << 8) |
214 (((uint32_t) base
[2]) << 16) |
215 (((uint32_t) base
[3]) << 24);
219 processor_t
*debug_module_t::current_proc() const
221 processor_t
*proc
= NULL
;
223 proc
= sim
->get_core(dmcontrol
.hartsel
);
224 } catch (const std::out_of_range
&) {
229 unsigned debug_module_t::sb_access_bits()
231 return 8 << sbcs
.sbaccess
;
234 void debug_module_t::sb_autoincrement()
236 if (!sbcs
.autoincrement
)
239 uint64_t value
= sbaddress
[0] + sb_access_bits() / 8;
240 sbaddress
[0] = value
;
241 uint32_t carry
= value
>> 32;
243 value
= sbaddress
[1] + carry
;
244 sbaddress
[1] = value
;
247 value
= sbaddress
[2] + carry
;
248 sbaddress
[2] = value
;
251 sbaddress
[3] += carry
;
254 void debug_module_t::sb_read()
256 reg_t address
= ((uint64_t) sbaddress
[1] << 32) | sbaddress
[0];
257 D(fprintf(stderr
, "sb_read() @ 0x%lx\n", address
));
259 switch (sbcs
.sbaccess
) {
261 sbdata
[0] = sim
->debug_mmu
->load_uint8(address
);
264 sbdata
[0] = sim
->debug_mmu
->load_uint16(address
);
267 sbdata
[0] = sim
->debug_mmu
->load_uint32(address
);
268 D(fprintf(stderr
, " -> 0x%x\n", sbdata
[0]));
272 uint64_t value
= sim
->debug_mmu
->load_uint32(address
);
274 sbdata
[1] = value
>> 32;
281 } catch (trap_load_access_fault
& t
) {
286 void debug_module_t::sb_write()
288 reg_t address
= ((uint64_t) sbaddress
[1] << 32) | sbaddress
[0];
289 D(fprintf(stderr
, "sb_write() 0x%x @ 0x%lx\n", sbdata
[0], address
));
290 switch (sbcs
.sbaccess
) {
292 sim
->debug_mmu
->store_uint8(address
, sbdata
[0]);
295 sim
->debug_mmu
->store_uint16(address
, sbdata
[0]);
298 sim
->debug_mmu
->store_uint32(address
, sbdata
[0]);
301 sim
->debug_mmu
->store_uint64(address
,
302 (((uint64_t) sbdata
[1]) << 32) | sbdata
[0]);
310 bool debug_module_t::dmi_read(unsigned address
, uint32_t *value
)
313 D(fprintf(stderr
, "dmi_read(0x%x) -> ", address
));
314 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
315 unsigned i
= address
- DMI_DATA0
;
316 result
= read32(dmdata
, i
);
317 if (abstractcs
.busy
) {
319 fprintf(stderr
, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address
, i
);
322 if (abstractcs
.busy
&& abstractcs
.cmderr
== CMDERR_NONE
) {
323 abstractcs
.cmderr
= CMDERR_BUSY
;
326 if (!abstractcs
.busy
&& ((abstractauto
.autoexecdata
>> i
) & 1)) {
327 perform_abstract_command();
329 } else if (address
>= DMI_PROGBUF0
&& address
< DMI_PROGBUF0
+ progbufsize
) {
330 unsigned i
= address
- DMI_PROGBUF0
;
331 result
= read32(program_buffer
, i
);
332 if (abstractcs
.busy
) {
334 fprintf(stderr
, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address
, i
);
336 if (!abstractcs
.busy
&& ((abstractauto
.autoexecprogbuf
>> i
) & 1)) {
337 perform_abstract_command();
344 processor_t
*proc
= current_proc();
346 dmcontrol
.haltreq
= proc
->halt_request
;
348 result
= set_field(result
, DMI_DMCONTROL_HALTREQ
, dmcontrol
.haltreq
);
349 result
= set_field(result
, DMI_DMCONTROL_RESUMEREQ
, dmcontrol
.resumereq
);
350 result
= set_field(result
, ((1L<<hartsellen
)-1) <<
351 DMI_DMCONTROL_HARTSEL_OFFSET
, dmcontrol
.hartsel
);
352 result
= set_field(result
, DMI_DMCONTROL_HARTRESET
, dmcontrol
.hartreset
);
353 result
= set_field(result
, DMI_DMCONTROL_NDMRESET
, dmcontrol
.ndmreset
);
354 result
= set_field(result
, DMI_DMCONTROL_DMACTIVE
, dmcontrol
.dmactive
);
359 processor_t
*proc
= current_proc();
361 dmstatus
.allnonexistant
= false;
362 dmstatus
.allunavail
= false;
363 dmstatus
.allrunning
= false;
364 dmstatus
.allhalted
= false;
365 dmstatus
.allresumeack
= false;
367 if (halted
[dmcontrol
.hartsel
]) {
368 dmstatus
.allhalted
= true;
370 dmstatus
.allrunning
= true;
373 dmstatus
.allnonexistant
= true;
375 dmstatus
.anynonexistant
= dmstatus
.allnonexistant
;
376 dmstatus
.anyunavail
= dmstatus
.allunavail
;
377 dmstatus
.anyrunning
= dmstatus
.allrunning
;
378 dmstatus
.anyhalted
= dmstatus
.allhalted
;
380 if (resumeack
[dmcontrol
.hartsel
]) {
381 dmstatus
.allresumeack
= true;
383 dmstatus
.allresumeack
= false;
386 dmstatus
.allresumeack
= false;
389 result
= set_field(result
, DMI_DMSTATUS_IMPEBREAK
,
391 result
= set_field(result
, DMI_DMSTATUS_ALLNONEXISTENT
, dmstatus
.allnonexistant
);
392 result
= set_field(result
, DMI_DMSTATUS_ALLUNAVAIL
, dmstatus
.allunavail
);
393 result
= set_field(result
, DMI_DMSTATUS_ALLRUNNING
, dmstatus
.allrunning
);
394 result
= set_field(result
, DMI_DMSTATUS_ALLHALTED
, dmstatus
.allhalted
);
395 result
= set_field(result
, DMI_DMSTATUS_ALLRESUMEACK
, dmstatus
.allresumeack
);
396 result
= set_field(result
, DMI_DMSTATUS_ANYNONEXISTENT
, dmstatus
.anynonexistant
);
397 result
= set_field(result
, DMI_DMSTATUS_ANYUNAVAIL
, dmstatus
.anyunavail
);
398 result
= set_field(result
, DMI_DMSTATUS_ANYRUNNING
, dmstatus
.anyrunning
);
399 result
= set_field(result
, DMI_DMSTATUS_ANYHALTED
, dmstatus
.anyhalted
);
400 result
= set_field(result
, DMI_DMSTATUS_ANYRESUMEACK
, dmstatus
.anyresumeack
);
401 result
= set_field(result
, DMI_DMSTATUS_AUTHENTICATED
, dmstatus
.authenticated
);
402 result
= set_field(result
, DMI_DMSTATUS_AUTHBUSY
, dmstatus
.authbusy
);
403 result
= set_field(result
, DMI_DMSTATUS_VERSION
, dmstatus
.version
);
407 result
= set_field(result
, DMI_ABSTRACTCS_CMDERR
, abstractcs
.cmderr
);
408 result
= set_field(result
, DMI_ABSTRACTCS_BUSY
, abstractcs
.busy
);
409 result
= set_field(result
, DMI_ABSTRACTCS_DATACOUNT
, abstractcs
.datacount
);
410 result
= set_field(result
, DMI_ABSTRACTCS_PROGBUFSIZE
,
411 abstractcs
.progbufsize
);
413 case DMI_ABSTRACTAUTO
:
414 result
= set_field(result
, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF
, abstractauto
.autoexecprogbuf
);
415 result
= set_field(result
, DMI_ABSTRACTAUTO_AUTOEXECDATA
, abstractauto
.autoexecdata
);
421 result
= set_field(result
, DMI_HARTINFO_NSCRATCH
, 1);
422 result
= set_field(result
, DMI_HARTINFO_DATAACCESS
, 1);
423 result
= set_field(result
, DMI_HARTINFO_DATASIZE
, abstractcs
.datacount
);
424 result
= set_field(result
, DMI_HARTINFO_DATAADDR
, debug_data_start
);
427 result
= set_field(result
, DMI_SBCS_SBVERSION
, sbcs
.version
);
428 result
= set_field(result
, DMI_SBCS_SBREADONADDR
, sbcs
.readonaddr
);
429 result
= set_field(result
, DMI_SBCS_SBACCESS
, sbcs
.sbaccess
);
430 result
= set_field(result
, DMI_SBCS_SBAUTOINCREMENT
, sbcs
.autoincrement
);
431 result
= set_field(result
, DMI_SBCS_SBREADONDATA
, sbcs
.readondata
);
432 result
= set_field(result
, DMI_SBCS_SBERROR
, sbcs
.error
);
433 result
= set_field(result
, DMI_SBCS_SBASIZE
, sbcs
.asize
);
434 result
= set_field(result
, DMI_SBCS_SBACCESS128
, sbcs
.access128
);
435 result
= set_field(result
, DMI_SBCS_SBACCESS64
, sbcs
.access64
);
436 result
= set_field(result
, DMI_SBCS_SBACCESS32
, sbcs
.access32
);
437 result
= set_field(result
, DMI_SBCS_SBACCESS16
, sbcs
.access16
);
438 result
= set_field(result
, DMI_SBCS_SBACCESS8
, sbcs
.access8
);
441 result
= sbaddress
[0];
444 result
= sbaddress
[1];
447 result
= sbaddress
[2];
450 result
= sbaddress
[3];
454 if (sbcs
.error
== 0) {
456 if (sbcs
.readondata
) {
472 D(fprintf(stderr
, "Unexpected. Returning Error."));
476 D(fprintf(stderr
, "0x%x\n", result
));
481 bool debug_module_t::perform_abstract_command()
483 if (abstractcs
.cmderr
!= CMDERR_NONE
)
485 if (abstractcs
.busy
) {
486 abstractcs
.cmderr
= CMDERR_BUSY
;
490 if ((command
>> 24) == 0) {
492 unsigned size
= get_field(command
, AC_ACCESS_REGISTER_SIZE
);
493 bool write
= get_field(command
, AC_ACCESS_REGISTER_WRITE
);
494 unsigned regno
= get_field(command
, AC_ACCESS_REGISTER_REGNO
);
496 if (!halted
[dmcontrol
.hartsel
]) {
497 abstractcs
.cmderr
= CMDERR_HALTRESUME
;
501 if (get_field(command
, AC_ACCESS_REGISTER_TRANSFER
)) {
503 if (regno
< 0x1000 || regno
>= 0x1020) {
504 abstractcs
.cmderr
= CMDERR_NOTSUP
;
508 unsigned regnum
= regno
- 0x1000;
513 write32(debug_abstract
, 0, lw(regnum
, ZERO
, debug_data_start
));
515 write32(debug_abstract
, 0, sw(regnum
, ZERO
, debug_data_start
));
519 write32(debug_abstract
, 0, ld(regnum
, ZERO
, debug_data_start
));
521 write32(debug_abstract
, 0, sd(regnum
, ZERO
, debug_data_start
));
526 write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
528 write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
532 abstractcs
.cmderr
= CMDERR_NOTSUP
;
537 write32(debug_abstract
, 0, addi(ZERO
, ZERO
, 0));
540 if (get_field(command
, AC_ACCESS_REGISTER_POSTEXEC
)) {
541 // Since the next instruction is what we will use, just use nother NOP
543 write32(debug_abstract
, 1, addi(ZERO
, ZERO
, 0));
545 write32(debug_abstract
, 1, ebreak());
548 debug_rom_flags
[dmcontrol
.hartsel
] |= 1 << DEBUG_ROM_FLAG_GO
;
550 abstractcs
.busy
= true;
552 abstractcs
.cmderr
= CMDERR_NOTSUP
;
557 bool debug_module_t::dmi_write(unsigned address
, uint32_t value
)
559 D(fprintf(stderr
, "dmi_write(0x%x, 0x%x)\n", address
, value
));
560 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
561 unsigned i
= address
- DMI_DATA0
;
562 if (!abstractcs
.busy
)
563 write32(dmdata
, address
- DMI_DATA0
, value
);
565 if (abstractcs
.busy
&& abstractcs
.cmderr
== CMDERR_NONE
) {
566 abstractcs
.cmderr
= CMDERR_BUSY
;
569 if (!abstractcs
.busy
&& ((abstractauto
.autoexecdata
>> i
) & 1)) {
570 perform_abstract_command();
574 } else if (address
>= DMI_PROGBUF0
&& address
< DMI_PROGBUF0
+ progbufsize
) {
575 unsigned i
= address
- DMI_PROGBUF0
;
577 if (!abstractcs
.busy
)
578 write32(program_buffer
, i
, value
);
580 if (!abstractcs
.busy
&& ((abstractauto
.autoexecprogbuf
>> i
) & 1)) {
581 perform_abstract_command();
589 if (!dmcontrol
.dmactive
&& get_field(value
, DMI_DMCONTROL_DMACTIVE
))
591 dmcontrol
.dmactive
= get_field(value
, DMI_DMCONTROL_DMACTIVE
);
592 if (dmcontrol
.dmactive
) {
593 dmcontrol
.haltreq
= get_field(value
, DMI_DMCONTROL_HALTREQ
);
594 dmcontrol
.resumereq
= get_field(value
, DMI_DMCONTROL_RESUMEREQ
);
595 dmcontrol
.hartreset
= get_field(value
, DMI_DMCONTROL_HARTRESET
);
596 dmcontrol
.ndmreset
= get_field(value
, DMI_DMCONTROL_NDMRESET
);
597 dmcontrol
.hartsel
= get_field(value
, ((1L<<hartsellen
)-1) <<
598 DMI_DMCONTROL_HARTSEL_OFFSET
);
600 processor_t
*proc
= current_proc();
602 proc
->halt_request
= dmcontrol
.haltreq
;
603 if (dmcontrol
.resumereq
) {
604 debug_rom_flags
[dmcontrol
.hartsel
] |= (1 << DEBUG_ROM_FLAG_RESUME
);
605 resumeack
[dmcontrol
.hartsel
] = false;
607 if (dmcontrol
.hartreset
) {
611 if (dmcontrol
.ndmreset
) {
612 for (size_t i
= 0; i
< sim
->nprocs(); i
++) {
613 proc
= sim
->get_core(i
);
622 return perform_abstract_command();
625 abstractcs
.cmderr
= (cmderr_t
) (((uint32_t) (abstractcs
.cmderr
)) & (~(uint32_t)(get_field(value
, DMI_ABSTRACTCS_CMDERR
))));
628 case DMI_ABSTRACTAUTO
:
629 abstractauto
.autoexecprogbuf
= get_field(value
,
630 DMI_ABSTRACTAUTO_AUTOEXECPROGBUF
);
631 abstractauto
.autoexecdata
= get_field(value
,
632 DMI_ABSTRACTAUTO_AUTOEXECDATA
);
635 sbcs
.readonaddr
= get_field(value
, DMI_SBCS_SBREADONADDR
);
636 sbcs
.sbaccess
= get_field(value
, DMI_SBCS_SBACCESS
);
637 sbcs
.autoincrement
= get_field(value
, DMI_SBCS_SBAUTOINCREMENT
);
638 sbcs
.readondata
= get_field(value
, DMI_SBCS_SBREADONDATA
);
639 sbcs
.error
&= ~get_field(value
, DMI_SBCS_SBERROR
);
642 sbaddress
[0] = value
;
643 if (sbcs
.error
== 0 && sbcs
.readonaddr
) {
648 sbaddress
[1] = value
;
651 sbaddress
[2] = value
;
654 sbaddress
[3] = value
;
658 if (sbcs
.error
== 0) {
660 if (sbcs
.autoincrement
&& sbcs
.error
== 0) {