1 // See LICENSE for license details.
2 #ifndef _RISCV_DEBUG_MODULE_H
3 #define _RISCV_DEBUG_MODULE_H
19 HARTSTATUS_UNAVAILABLE
,
47 CMDERR_HALTRESUME
= 4,
54 class debug_module_data_t
: public abstract_device_t
57 debug_module_data_t();
59 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
60 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
62 uint32_t read32(reg_t addr
) const;
63 void write32(reg_t addr
, uint32_t value
);
65 uint8_t data
[DEBUG_EXCHANGE_SIZE
];
68 class debug_module_t
: public abstract_device_t
71 debug_module_t(sim_t
*sim
);
73 void add_device(bus_t
*bus
);
75 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
76 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
78 void set_interrupt(uint32_t hartid
) {
79 interrupt
.insert(hartid
);
81 void clear_interrupt(uint32_t hartid
) {
82 interrupt
.erase(hartid
);
84 bool get_interrupt(uint32_t hartid
) const {
85 return interrupt
.find(hartid
) != interrupt
.end();
88 void set_halt_notification(uint32_t hartid
) {
89 halt_notification
.insert(hartid
);
91 void clear_halt_notification(uint32_t hartid
) {
92 halt_notification
.erase(hartid
);
94 bool get_halt_notification(uint32_t hartid
) const {
95 return halt_notification
.find(hartid
) != halt_notification
.end();
98 // Debug Module Interface that the debugger (in our case through JTAG DTM)
99 // uses to access the DM.
100 // Return true for success, false for failure.
101 bool dmi_read(unsigned address
, uint32_t *value
);
102 bool dmi_write(unsigned address
, uint32_t value
);
105 static const unsigned progsize
= 8;
108 // Track which interrupts from module to debugger are set.
109 std::set
<uint32_t> interrupt
;
110 // Track which halt notifications from debugger to module are set.
111 std::set
<uint32_t> halt_notification
;
113 uint8_t debug_rom_entry
[DEBUG_ROM_ENTRY_SIZE
];
114 uint8_t debug_rom_code
[DEBUG_ROM_CODE_SIZE
];
115 uint8_t debug_rom_exception
[DEBUG_ROM_EXCEPTION_SIZE
];
116 uint8_t program_buffer
[progsize
* 4];
118 debug_module_data_t dmdata
;
119 // Instruction that will be placed at the current hart's ROM entry address
120 // after the current action has completed.
121 uint32_t next_action
;
122 bool action_executed
;
124 void write32(uint8_t *rom
, unsigned int index
, uint32_t value
);
125 uint32_t read32(uint8_t *rom
, unsigned int index
);
127 dmcontrol_t dmcontrol
;
128 abstractcs_t abstractcs
;
131 processor_t
*current_proc() const;
133 bool perform_abstract_command();