1 #ifndef _RISCV_DECODE_H
2 #define _RISCV_DECODE_H
4 #define __STDC_LIMIT_MACROS
9 typedef int int128_t
__attribute__((mode(TI
)));
10 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
12 typedef int64_t sreg_t
;
13 typedef uint64_t reg_t
;
14 typedef uint64_t freg_t
;
16 const int OPCODE_BITS
= 7;
18 const int XPRID_BITS
= 5;
19 const int NXPR
= 1 << XPRID_BITS
;
21 const int FPR_BITS
= 64;
22 const int FPRID_BITS
= 5;
23 const int NFPR
= 1 << FPRID_BITS
;
25 const int IMM_BITS
= 12;
26 const int IMMLO_BITS
= 7;
27 const int TARGET_BITS
= 25;
28 const int FUNCT_BITS
= 3;
29 const int FUNCTR_BITS
= 7;
30 const int FFUNCT_BITS
= 2;
31 const int RM_BITS
= 3;
32 const int BIGIMM_BITS
= 20;
33 const int BRANCH_ALIGN_BITS
= 1;
34 const int JUMP_ALIGN_BITS
= 1;
36 #define SR_ET 0x0000000000000001ULL
37 #define SR_PS 0x0000000000000004ULL
38 #define SR_S 0x0000000000000008ULL
39 #define SR_EF 0x0000000000000010ULL
40 #define SR_UX 0x0000000000000020ULL
41 #define SR_SX 0x0000000000000040ULL
42 #define SR_IM 0x000000000000FF00ULL
43 #define SR_ZERO ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
53 #define FSR_RD_SHIFT 5
54 #define FSR_RD (0x7 << FSR_RD_SHIFT)
62 #define FSR_AEXC_SHIFT 0
63 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
64 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
65 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
66 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
67 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
68 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
70 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
72 // note: bit fields are in little-endian order
75 unsigned opcode
: OPCODE_BITS
;
76 unsigned funct
: FUNCT_BITS
;
77 signed imm12
: IMM_BITS
;
78 unsigned rs1
: XPRID_BITS
;
79 unsigned rd
: XPRID_BITS
;
84 unsigned opcode
: OPCODE_BITS
;
85 unsigned funct
: FUNCT_BITS
;
86 unsigned immlo
: IMMLO_BITS
;
87 unsigned rs2
: XPRID_BITS
;
88 unsigned rs1
: XPRID_BITS
;
89 signed immhi
: IMM_BITS
-IMMLO_BITS
;
94 unsigned jump_opcode
: OPCODE_BITS
;
95 signed target
: TARGET_BITS
;
100 unsigned opcode
: OPCODE_BITS
;
101 unsigned funct
: FUNCT_BITS
;
102 unsigned functr
: FUNCTR_BITS
;
103 unsigned rs2
: XPRID_BITS
;
104 unsigned rs1
: XPRID_BITS
;
105 unsigned rd
: XPRID_BITS
;
110 unsigned opcode
: OPCODE_BITS
;
111 unsigned bigimm
: BIGIMM_BITS
;
112 unsigned rd
: XPRID_BITS
;
117 unsigned opcode
: OPCODE_BITS
;
118 unsigned ffunct
: FFUNCT_BITS
;
119 unsigned rm
: RM_BITS
;
120 unsigned rs3
: FPRID_BITS
;
121 unsigned rs2
: FPRID_BITS
;
122 unsigned rs1
: FPRID_BITS
;
123 unsigned rd
: FPRID_BITS
;
139 class trace_writeback
142 trace_writeback(reg_t
* _rf
, int _rd
) : rf(_rf
), rd(_rd
) {}
144 reg_t
operator = (reg_t rhs
)
146 printf("R[%x] <= %llx\n",rd
,(long long)rhs
);
156 #define do_writeback(rf,rd) trace_writeback(rf,rd)
158 #define do_writeback(rf,rd) rf[rd]
161 // helpful macros, etc
162 #define RS1 XPR[insn.rtype.rs1]
163 #define RS2 XPR[insn.rtype.rs2]
164 #define RD do_writeback(XPR,insn.rtype.rd)
165 #define RA do_writeback(XPR,1)
166 #define FRS1 FPR[insn.ftype.rs1]
167 #define FRS2 FPR[insn.ftype.rs2]
168 #define FRS3 FPR[insn.ftype.rs3]
169 #define FRD FPR[insn.ftype.rd]
170 #define BIGIMM insn.ltype.bigimm
171 #define SIMM insn.itype.imm12
172 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
173 #define SHAMT (insn.itype.imm12 & 0x3F)
174 #define SHAMTW (insn.itype.imm12 & 0x1F)
175 #define TARGET insn.jtype.target
176 #define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
177 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
178 #define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \
179 ((fsr & FSR_RD) >> FSR_RD_SHIFT))
181 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
182 #define xpr64 (xprlen == 64)
183 #define require_xpr64 if(!xpr64) throw trap_illegal_instruction
184 #define require_xpr32 if(xpr64) throw trap_illegal_instruction
185 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
186 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
187 #define set_fp_exceptions ({ set_fsr(fsr | \
188 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
189 softfloat_exceptionFlags = 0; })
191 static inline sreg_t
sext32(int32_t arg
)
196 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))