1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #if (-1 != ~0) || ((-1 >> 1) != -1)
7 # error spike requires a two''s-complement c++ implementation
10 #ifdef WORDS_BIGENDIAN
11 # error spike requires a little-endian host
22 typedef int64_t sreg_t
;
23 typedef uint64_t reg_t
;
24 typedef uint64_t freg_t
;
28 const int NCSR
= 4096;
39 #define FSR_RD_SHIFT 5
40 #define FSR_RD (0x7 << FSR_RD_SHIFT)
48 #define FSR_AEXC_SHIFT 0
49 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
50 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
51 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
52 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
53 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
54 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
56 #define insn_length(x) \
57 (((x) & 0x03) < 0x03 ? 2 : \
58 ((x) & 0x1f) < 0x1f ? 4 : \
59 ((x) & 0x3f) < 0x3f ? 6 : \
61 #define MAX_INSN_LENGTH 8
64 typedef uint64_t insn_bits_t
;
69 insn_t(insn_bits_t bits
) : b(bits
) {}
70 insn_bits_t
bits() { return b
; }
71 int length() { return insn_length(b
); }
72 int64_t i_imm() { return int64_t(b
) >> 20; }
73 int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
74 int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
75 int64_t u_imm() { return int64_t(b
) >> 12 << 12; }
76 int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
77 uint64_t rd() { return x(7, 5); }
78 uint64_t rs1() { return x(15, 5); }
79 uint64_t rs2() { return x(20, 5); }
80 uint64_t rs3() { return x(27, 5); }
81 uint64_t rm() { return x(12, 3); }
82 uint64_t csr() { return x(20, 12); }
84 int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
85 int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
86 int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
87 int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }
88 int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
89 int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
90 int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
91 int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
92 int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
93 int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
94 int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }
95 int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }
96 int64_t rvc_simm3() { return x(10, 3); }
97 uint64_t rvc_rd() { return rd(); }
98 uint64_t rvc_rs1() { return rd(); }
99 uint64_t rvc_rs2() { return x(2, 5); }
100 uint64_t rvc_rs1s() { return 8 + x(7, 3); }
101 uint64_t rvc_rs2s() { return 8 + x(2, 3); }
104 uint64_t x(int lo
, int len
) { return (b
>> lo
) & ((insn_bits_t(1) << len
)-1); }
105 uint64_t xs(int lo
, int len
) { return int64_t(b
) << (64-lo
-len
) >> (64-len
); }
106 uint64_t imm_sign() { return xs(63, 1); }
109 template <class T
, size_t N
, bool zero_reg
>
113 void write(size_t i
, T value
)
115 if (!zero_reg
|| i
!= 0)
118 const T
& operator [] (size_t i
) const
126 // helpful macros, etc
127 #define MMU (*p->get_mmu())
128 #define STATE (*p->get_state())
129 #define READ_REG(reg) STATE.XPR[reg]
130 #define READ_FREG(reg) STATE.FPR[reg]
131 #define RS1 READ_REG(insn.rs1())
132 #define RS2 READ_REG(insn.rs2())
133 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
135 #ifndef RISCV_ENABLE_COMMITLOG
136 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
137 # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value)
139 # define WRITE_REG(reg, value) ({ \
140 reg_t wdata = (value); /* value may have side effects */ \
141 STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
142 STATE.XPR.write(reg, wdata); \
144 # define WRITE_FREG(reg, value) ({ \
145 freg_t wdata = (value); /* value may have side effects */ \
146 STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
147 DO_WRITE_FREG(reg, wdata); \
152 #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
153 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
154 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
155 #define RVC_RS1 READ_REG(insn.rvc_rs1())
156 #define RVC_RS2 READ_REG(insn.rvc_rs2())
157 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
158 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
159 #define RVC_FRS2 READ_FREG(insn.rvc_rs2())
160 #define RVC_FRS2S READ_FREG(insn.rvc_rs2s())
161 #define RVC_SP READ_REG(X_SP)
164 #define FRS1 READ_FREG(insn.rs1())
165 #define FRS2 READ_FREG(insn.rs2())
166 #define FRS3 READ_FREG(insn.rs3())
167 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
168 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
169 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
170 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
172 #define SHAMT (insn.i_imm() & 0x3F)
173 #define BRANCH_TARGET (pc + insn.sb_imm())
174 #define JUMP_TARGET (pc + insn.uj_imm())
175 #define RM ({ int rm = insn.rm(); \
176 if(rm == 7) rm = STATE.frm; \
177 if(rm > 4) throw trap_illegal_instruction(0); \
180 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
181 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
183 #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0)
184 #define require_privilege(p) require(STATE.prv >= (p))
185 #define require_rv64 require(xlen == 64)
186 #define require_rv32 require(xlen == 32)
187 #define require_extension(s) require(p->supports_extension(s))
188 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
189 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
191 #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
193 STATE.fflags |= softfloat_exceptionFlags; \
195 softfloat_exceptionFlags = 0; })
197 #define sext32(x) ((sreg_t)(int32_t)(x))
198 #define zext32(x) ((reg_t)(uint32_t)(x))
199 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
200 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
203 do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
204 throw trap_instruction_address_misaligned(x); \
205 npc = sext_xlen(x); \
208 #define set_pc_and_serialize(x) \
209 do { reg_t __npc = (x); \
210 set_pc(__npc); /* check alignment */ \
211 npc = PC_SERIALIZE_AFTER; \
215 /* Sentinel PC values to serialize simulator pipeline */
216 #define PC_SERIALIZE_BEFORE 3
217 #define PC_SERIALIZE_AFTER 5
218 #define invalid_pc(pc) ((pc) & 1)
220 /* Convenience wrappers to simplify softfloat code sequences */
221 #define f32(x) ((float32_t){(uint32_t)x})
222 #define f64(x) ((float64_t){(uint64_t)x})
224 #define validate_csr(which, write) ({ \
225 if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
226 STATE.serialized = false; \
227 unsigned csr_priv = get_field((which), 0x300); \
228 unsigned csr_read_only = get_field((which), 0xC00) == 3; \
229 if (((write) && csr_read_only) || STATE.prv < csr_priv) \
230 throw trap_illegal_instruction(0); \
233 #define DEBUG_START 0x100
234 #define DEBUG_ROM_START 0x800
235 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
236 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
237 #define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len)
238 #define DEBUG_RAM_START 0x400
239 #define DEBUG_RAM_SIZE 64
240 #define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE)
241 #define DEBUG_END 0xfff
242 #define DEBUG_CLEARDEBINT 0x100
243 #define DEBUG_SETHALTNOT 0x10c
244 #define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1)