1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #define __STDC_LIMIT_MACROS
12 typedef int int128_t
__attribute__((mode(TI
)));
13 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
15 typedef int64_t sreg_t
;
16 typedef uint64_t reg_t
;
17 typedef uint64_t freg_t
;
19 const int OPCODE_BITS
= 7;
21 const int XPRID_BITS
= 5;
22 const int NXPR
= 1 << XPRID_BITS
;
24 const int FPR_BITS
= 64;
25 const int FPRID_BITS
= 5;
26 const int NFPR
= 1 << FPRID_BITS
;
28 const int IMM_BITS
= 12;
29 const int IMMLO_BITS
= 7;
30 const int TARGET_BITS
= 25;
31 const int FUNCT_BITS
= 3;
32 const int FUNCTR_BITS
= 7;
33 const int FFUNCT_BITS
= 2;
34 const int RM_BITS
= 3;
35 const int BIGIMM_BITS
= 20;
36 const int BRANCH_ALIGN_BITS
= 1;
37 const int JUMP_ALIGN_BITS
= 1;
45 #define FSR_RD_SHIFT 5
46 #define FSR_RD (0x7 << FSR_RD_SHIFT)
54 #define FSR_AEXC_SHIFT 0
55 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
56 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
57 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
58 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
59 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
60 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
62 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
64 // note: bit fields are in little-endian order
67 unsigned opcode
: OPCODE_BITS
;
68 unsigned funct
: FUNCT_BITS
;
69 signed imm12
: IMM_BITS
;
70 unsigned rs1
: XPRID_BITS
;
71 unsigned rd
: XPRID_BITS
;
76 unsigned opcode
: OPCODE_BITS
;
77 unsigned funct
: FUNCT_BITS
;
78 unsigned immlo
: IMMLO_BITS
;
79 unsigned rs2
: XPRID_BITS
;
80 unsigned rs1
: XPRID_BITS
;
81 signed immhi
: IMM_BITS
-IMMLO_BITS
;
86 unsigned jump_opcode
: OPCODE_BITS
;
87 signed target
: TARGET_BITS
;
92 unsigned opcode
: OPCODE_BITS
;
93 unsigned funct
: FUNCT_BITS
;
94 unsigned functr
: FUNCTR_BITS
;
95 unsigned rs2
: XPRID_BITS
;
96 unsigned rs1
: XPRID_BITS
;
97 unsigned rd
: XPRID_BITS
;
102 unsigned opcode
: OPCODE_BITS
;
103 unsigned bigimm
: BIGIMM_BITS
;
104 unsigned rd
: XPRID_BITS
;
109 unsigned opcode
: OPCODE_BITS
;
110 unsigned ffunct
: FFUNCT_BITS
;
111 unsigned rm
: RM_BITS
;
112 unsigned rs3
: FPRID_BITS
;
113 unsigned rs2
: FPRID_BITS
;
114 unsigned rs1
: FPRID_BITS
;
115 unsigned rd
: FPRID_BITS
;
133 write_port_t(T
& _t
) : t(_t
) {}
134 T
& operator = (const T
& rhs
)
145 template <class T
, size_t N
, bool zero_reg
>
151 memset(data
, 0, sizeof(data
));
153 write_port_t
<T
> write_port(size_t i
)
155 return write_port_t
<T
>(data
[i
]);
157 const T
& operator [] (size_t i
) const
160 const_cast<T
&>(data
[0]) = 0;
167 #define throw_illegal_instruction \
168 ({ if (utmode) throw trap_vector_illegal_instruction; \
169 else throw trap_illegal_instruction; })
171 // helpful macros, etc
172 #define RS1 XPR[insn.rtype.rs1]
173 #define RS2 XPR[insn.rtype.rs2]
174 #define RD XPR.write_port(insn.rtype.rd)
175 #define RA XPR.write_port(1)
176 #define FRS1 FPR[insn.ftype.rs1]
177 #define FRS2 FPR[insn.ftype.rs2]
178 #define FRS3 FPR[insn.ftype.rs3]
179 #define FRD FPR.write_port(insn.ftype.rd)
180 #define BIGIMM insn.ltype.bigimm
181 #define SIMM insn.itype.imm12
182 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
183 #define SHAMT (insn.itype.imm12 & 0x3F)
184 #define SHAMTW (insn.itype.imm12 & 0x1F)
185 #define TARGET insn.jtype.target
186 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
187 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
188 #define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
189 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
190 #define RM ({ int rm = insn.ftype.rm; \
191 if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
192 if(rm > 4) throw_illegal_instruction; \
195 #define xpr64 (xprlen == 64)
197 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
198 #define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
199 #define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
200 #ifndef RISCV_ENABLE_FPU
201 # define require_fp throw trap_illegal_instruction
203 # define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
205 #ifndef RISCV_ENABLE_VEC
206 # define require_vector throw trap_illegal_instruction
208 # define require_vector \
209 ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
210 else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
214 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
215 #define set_fp_exceptions ({ set_fsr(fsr | \
216 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
217 softfloat_exceptionFlags = 0; })
219 #define sext32(x) ((sreg_t)(int32_t)(x))
220 #define zext32(x) ((reg_t)(uint32_t)(x))
221 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
222 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
226 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
227 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
228 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
230 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
231 #define CRD XPR.write_port(CRD_REGNUM)
232 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
233 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
234 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
235 #define CIMM5U ((insn.bits >> 5) & 0x1f)
236 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
237 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
238 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
239 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
241 static const int rvc_rs1_regmap
[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
242 #define rvc_rd_regmap rvc_rs1_regmap
243 #define rvc_rs2b_regmap rvc_rs1_regmap
244 static const int rvc_rs2_regmap
[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
245 #define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
246 #define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
247 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
248 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
249 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
250 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
255 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
256 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
257 #define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
258 #define UT_RA(idx) uts[idx]->XPR.write_port(1)
259 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
260 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
261 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
262 #define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
263 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
264 ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
266 #define UT_LOOP_START for (int i=0;i<VL; i++) {
267 #define UT_LOOP_END }
268 #define UT_LOOP_RS1 UT_RS1(i)
269 #define UT_LOOP_RS2 UT_RS2(i)
270 #define UT_LOOP_RD UT_RD(i)
271 #define UT_LOOP_RA UT_RA(i)
272 #define UT_LOOP_FRS1 UT_FRS1(i)
273 #define UT_LOOP_FRS2 UT_FRS2(i)
274 #define UT_LOOP_FRS3 UT_FRS3(i)
275 #define UT_LOOP_FRD UT_FRD(i)
276 #define UT_LOOP_RM UT_RM(i)
278 #define VEC_LOAD(dst, func, inc) \
281 UT_LOOP_##dst = mmu.func(addr); \
285 #define VEC_STORE(src, func, inc) \
288 mmu.func(addr, UT_LOOP_##src); \