riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 typedef int int128_t __attribute__((mode(TI)));
   7 typedef unsigned int uint128_t __attribute__((mode(TI)));
   8
   9 #define support_64bit 1
  10 typedef int64_t sreg_t;
  11 typedef uint64_t reg_t;
  12 typedef uint64_t freg_t;
  13
  14 const int OPCODE_BITS = 7;
  15 const int JTYPE_OPCODE_BITS = 5;
  16
  17 const int GPR_BITS = 8*sizeof(reg_t);
  18 const int GPRID_BITS = 5;
  19 const int NGPR = 1 << GPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int TARGET_BITS = 27;
  27 const int SHAMT_BITS = 6;
  28 const int FUNCT_BITS = 3;
  29 const int FFUNCT_BITS = 5;
  30 const int BIGIMM_BITS = 20;
  31 const int BRANCH_ALIGN_BITS = 1;
  32 const int JUMP_ALIGN_BITS = 1;
  33
  34 #define SR_ET    0x0000000000000001ULL
  35 #define SR_PS    0x0000000000000004ULL
  36 #define SR_S     0x0000000000000008ULL
  37 #define SR_EF    0x0000000000000010ULL
  38 #define SR_UX    0x0000000000000020ULL
  39 #define SR_KX    0x0000000000000040ULL
  40 #define SR_IM    0x000000000000FF00ULL
  41 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_KX | SR_IM)
  42
  43 #define FP_RD_NE  0
  44 #define FP_RD_0   1
  45 #define FP_RD_DN  2
  46 #define FP_RD_UP  3
  47 #define FP_RD_NMM 4
  48 #define FSR_RD_SHIFT 10
  49 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  50
  51 #define FPEXC_NX 0x01
  52 #define FPEXC_UF 0x02
  53 #define FPEXC_OF 0x04
  54 #define FPEXC_DZ 0x02
  55 #define FPEXC_NV 0x10
  56
  57 #define FSR_AEXC_SHIFT 0
  58 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  59 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  60 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  61 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  62 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  63 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  64
  65 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  66
  67 // note: bit fields are in little-endian order
  68 struct itype_t
  69 {
  70   unsigned imm : IMM_BITS;
  71   unsigned funct : FUNCT_BITS;
  72   unsigned rb : GPRID_BITS;
  73   unsigned ra : GPRID_BITS;
  74   unsigned opcode : OPCODE_BITS;
  75 };
  76
  77 struct jtype_t
  78 {
  79   unsigned target : TARGET_BITS;
  80   unsigned jump_opcode : JTYPE_OPCODE_BITS;
  81 };
  82
  83 struct rtype_t
  84 {
  85   unsigned rc : GPRID_BITS;
  86   unsigned shamt : SHAMT_BITS;
  87   unsigned unused : 1;
  88   unsigned funct : FUNCT_BITS;
  89   unsigned rb : GPRID_BITS;
  90   unsigned ra : GPRID_BITS;
  91   unsigned opcode : OPCODE_BITS;
  92 };
  93
  94 struct btype_t
  95 {
  96   unsigned bigimm : BIGIMM_BITS;
  97   unsigned rt : GPRID_BITS;
  98   unsigned opcode : OPCODE_BITS;
  99 };
 100
 101 struct ftype_t
 102 {
 103   unsigned rc : FPRID_BITS;
 104   unsigned rd : FPRID_BITS;
 105   unsigned ffunct : FFUNCT_BITS;
 106   unsigned rb : FPRID_BITS;
 107   unsigned ra : FPRID_BITS;
 108   unsigned opcode : OPCODE_BITS;
 109 };
 110
 111 union insn_t
 112 {
 113   itype_t itype;
 114   jtype_t jtype;
 115   rtype_t rtype;
 116   btype_t btype;
 117   ftype_t ftype;
 118   uint32_t bits;
 119 };
 120
 121 // helpful macros, etc
 122 #define RA R[insn.rtype.ra]
 123 #define RB R[insn.rtype.rb]
 124 #define RC R[insn.rtype.rc]
 125 #define FRA FR[insn.ftype.ra]
 126 #define FRB FR[insn.ftype.rb]
 127 #define FRC FR[insn.ftype.rc]
 128 #define FRD FR[insn.ftype.rd]
 129 #define BIGIMM insn.btype.bigimm
 130 #define IMM insn.itype.imm
 131 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 132 #define SHAMT insn.rtype.shamt
 133 #define TARGET insn.jtype.target
 134 #define BRANCH_TARGET (pc + (SIMM << BRANCH_ALIGN_BITS))
 135 #define JUMP_TARGET ((pc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
 136
 137 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 138 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 139 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 140 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
 141 #define set_fp_exceptions ({ set_fsr(fsr | \
 142                                 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 143                              softfloat_exceptionFlags = 0; })
 144
 145 static inline sreg_t sext32(int32_t arg)
 146 {
 147   return arg;
 148 }
 149
 150 #endif