1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #if (-1 != ~0) || ((-1 >> 1) != -1)
7 # error spike requires a two''s-complement c++ implementation
17 typedef int64_t sreg_t
;
18 typedef uint64_t reg_t
;
19 typedef uint64_t freg_t
;
30 #define FSR_RD_SHIFT 5
31 #define FSR_RD (0x7 << FSR_RD_SHIFT)
39 #define FSR_AEXC_SHIFT 0
40 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
41 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
42 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
43 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
44 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
45 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
50 uint32_t bits() { return b
; }
51 int32_t i_imm() { return int32_t(b
) >> 20; }
52 int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
53 int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
54 int32_t u_imm() { return int32_t(b
) >> 12 << 12; }
55 int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
56 uint32_t rd() { return x(7, 5); }
57 uint32_t rs1() { return x(15, 5); }
58 uint32_t rs2() { return x(20, 5); }
59 uint32_t rs3() { return x(27, 5); }
60 uint32_t rm() { return x(12, 3); }
61 uint32_t csr() { return x(20, 12); }
64 uint32_t x(int lo
, int len
) { return b
<< (32-lo
-len
) >> (32-len
); }
65 uint32_t xs(int lo
, int len
) { return int32_t(b
) << (32-lo
-len
) >> (32-len
); }
66 uint32_t imm_sign() { return xs(31, 1); }
69 template <class T
, size_t N
, bool zero_reg
>
75 memset(data
, 0, sizeof(data
));
77 void write(size_t i
, T value
)
83 const T
& operator [] (size_t i
) const
91 // helpful macros, etc
92 #define MMU (*p->get_mmu())
93 #define STATE (*p->get_state())
94 #define RS1 STATE.XPR[insn.rs1()]
95 #define RS2 STATE.XPR[insn.rs2()]
96 #define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
98 #ifdef RISCV_ENABLE_COMMITLOG
100 #define WRITE_RD(value) ({ \
101 reg_t wdata = value; /* value is a func with side-effects */ \
102 STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
103 STATE.XPR.write(insn.rd(), wdata); \
107 #define FRS1 STATE.FPR[insn.rs1()]
108 #define FRS2 STATE.FPR[insn.rs2()]
109 #define FRS3 STATE.FPR[insn.rs3()]
110 #define WRITE_FRD(value) STATE.FPR.write(insn.rd(), value)
112 #ifdef RISCV_ENABLE_COMMITLOG
114 #define WRITE_FRD(value) ({ \
115 freg_t wdata = value; /* value is a func with side-effects */ \
116 STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
117 STATE.FPR.write(insn.rd(), wdata); \
121 #define SHAMT (insn.i_imm() & 0x3F)
122 #define BRANCH_TARGET (pc + insn.sb_imm())
123 #define JUMP_TARGET (pc + insn.uj_imm())
124 #define RM ({ int rm = insn.rm(); \
125 if(rm == 7) rm = STATE.frm; \
126 if(rm > 4) throw trap_illegal_instruction(); \
129 #define xpr64 (xprlen == 64)
131 #define require_supervisor if(unlikely(!(STATE.sr & SR_S))) throw trap_privileged_instruction()
132 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
133 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
134 #ifndef RISCV_ENABLE_FPU
135 # define require_fp throw trap_illegal_instruction()
137 # define require_fp if(unlikely(!(STATE.sr & SR_EF))) throw trap_fp_disabled()
139 #define require_accelerator if(unlikely(!(STATE.sr & SR_EA))) throw trap_accelerator_disabled()
141 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
142 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
143 softfloat_exceptionFlags = 0; })
145 #define sext32(x) ((sreg_t)(int32_t)(x))
146 #define zext32(x) ((reg_t)(uint32_t)(x))
147 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
148 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
150 #define insn_length(x) \
151 (((x) & 0x03) < 0x03 ? 2 : \
152 ((x) & 0x1f) < 0x1f ? 4 : \
153 ((x) & 0x3f) < 0x3f ? 6 : \
157 do { if ((x) & 3 /* For now... */) \
158 throw trap_instruction_address_misaligned(x); \
159 npc = sext_xprlen(x); \
162 #define validate_csr(which, write) ({ \
163 unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \
164 unsigned read_priv = ((which) >> 10) & 3; \
165 unsigned write_priv = (((which) >> 8) & 3); \
166 if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
167 if (my_priv < ((write) ? write_priv : read_priv)) \
168 throw trap_privileged_instruction(); \