1 // See LICENSE for license details.
8 static void commit_log_stash_privilege(state_t
* state
)
10 #ifdef RISCV_ENABLE_COMMITLOG
11 state
->last_inst_priv
= state
->prv
;
15 static void commit_log_print_insn(state_t
* state
, reg_t pc
, insn_t insn
)
17 #ifdef RISCV_ENABLE_COMMITLOG
18 int32_t priv
= state
->last_inst_priv
;
19 uint64_t mask
= (insn
.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn
.length() * 8))) - 1;
20 if (state
->log_reg_write
.addr
) {
21 fprintf(stderr
, "%1d 0x%016" PRIx64
" (0x%08" PRIx64
") %c%2" PRIu64
" 0x%016" PRIx64
"\n",
25 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
26 state
->log_reg_write
.addr
>> 1,
27 state
->log_reg_write
.data
);
29 fprintf(stderr
, "%1d 0x%016" PRIx64
" (0x%08" PRIx64
")\n", priv
, pc
, insn
.bits() & mask
);
31 state
->log_reg_write
.addr
= 0;
35 inline void processor_t::update_histogram(reg_t pc
)
37 #ifdef RISCV_ENABLE_HISTOGRAM
42 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
44 commit_log_stash_privilege(p
->get_state());
45 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
46 if (!invalid_pc(npc
)) {
47 commit_log_print_insn(p
->get_state(), pc
, fetch
.insn
);
48 p
->update_histogram(pc
);
53 // fetch/decode/execute loop
54 void processor_t::step(size_t n
)
56 while (run
&& n
> 0) {
61 #define advance_pc() \
62 if (unlikely(invalid_pc(pc))) { \
64 case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
65 case PC_SERIALIZE_AFTER: instret++; break; \
83 insn_fetch_t fetch
= mmu
->load_insn(pc
);
84 if (!state
.serialized
)
86 pc
= execute_insn(this, pc
, fetch
);
90 else while (instret
< n
)
92 size_t idx
= _mmu
->icache_index(pc
);
93 auto ic_entry
= _mmu
->access_icache(pc
);
95 #define ICACHE_ACCESS(i) { \
96 insn_fetch_t fetch = ic_entry->data; \
98 pc = execute_insn(this, pc, fetch); \
99 if (i == mmu_t::ICACHE_ENTRIES-1) break; \
100 if (unlikely(ic_entry->tag != pc)) goto miss; \
101 if (unlikely(instret+1 == n)) break; \
115 // refill I$ if it looks like there wasn't a taken branch
116 if (pc
> (ic_entry
-1)->tag
&& pc
<= (ic_entry
-1)->tag
+ MAX_INSN_LENGTH
)
117 _mmu
->refill_icache(pc
, ic_entry
);
126 state
.minstret
+= instret
;