1 // See LICENSE for license details.
9 static void commit_log_stash_privilege(processor_t
* p
)
11 #ifdef RISCV_ENABLE_COMMITLOG
12 state_t
* state
= p
->get_state();
13 state
->last_inst_priv
= state
->prv
;
14 state
->last_inst_xlen
= p
->get_xlen();
15 state
->last_inst_flen
= p
->get_flen();
19 static void commit_log_print_value(int width
, uint64_t hi
, uint64_t lo
)
23 fprintf(stderr
, "0x%04" PRIx16
, (uint16_t)lo
);
26 fprintf(stderr
, "0x%08" PRIx32
, (uint32_t)lo
);
29 fprintf(stderr
, "0x%016" PRIx64
, lo
);
32 fprintf(stderr
, "0x%016" PRIx64
"%016" PRIx64
, hi
, lo
);
39 static void commit_log_print_insn(state_t
* state
, reg_t pc
, insn_t insn
)
41 #ifdef RISCV_ENABLE_COMMITLOG
42 auto& reg
= state
->log_reg_write
;
43 int priv
= state
->last_inst_priv
;
44 int xlen
= state
->last_inst_xlen
;
45 int flen
= state
->last_inst_flen
;
47 fprintf(stderr
, "%1d ", priv
);
48 commit_log_print_value(xlen
, 0, pc
);
49 fprintf(stderr
, " (");
50 commit_log_print_value(insn
.length() * 8, 0, insn
.bits());
53 bool fp
= reg
.addr
& 1;
54 int rd
= reg
.addr
>> 1;
55 int size
= fp
? flen
: xlen
;
56 fprintf(stderr
, ") %c%2d ", fp
? 'f' : 'x', rd
);
57 commit_log_print_value(size
, reg
.data
.v
[1], reg
.data
.v
[0]);
58 fprintf(stderr
, "\n");
60 fprintf(stderr
, ")\n");
66 inline void processor_t::update_histogram(reg_t pc
)
68 #ifdef RISCV_ENABLE_HISTOGRAM
73 // This is expected to be inlined by the compiler so each use of execute_insn
74 // includes a duplicated body of the function to get separate fetch.func
76 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
78 commit_log_stash_privilege(p
);
79 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
80 if (!invalid_pc(npc
)) {
81 commit_log_print_insn(p
->get_state(), pc
, fetch
.insn
);
82 p
->update_histogram(pc
);
87 bool processor_t::slow_path()
89 return debug
|| state
.single_step
!= state
.STEP_NONE
|| state
.dcsr
.cause
;
92 // fetch/decode/execute loop
93 void processor_t::step(size_t n
)
95 if (state
.dcsr
.cause
== DCSR_CAUSE_NONE
) {
97 enter_debug_mode(DCSR_CAUSE_DEBUGINT
);
98 } // !!!The halt bit in DCSR is deprecated.
99 else if (state
.dcsr
.halt
) {
100 enter_debug_mode(DCSR_CAUSE_HALT
);
109 #define advance_pc() \
110 if (unlikely(invalid_pc(pc))) { \
112 case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
113 case PC_SERIALIZE_AFTER: n = ++instret; break; \
125 take_pending_interrupt();
127 if (unlikely(slow_path()))
131 if (unlikely(state
.single_step
== state
.STEP_STEPPING
)) {
132 state
.single_step
= state
.STEP_STEPPED
;
135 insn_fetch_t fetch
= mmu
->load_insn(pc
);
136 if (debug
&& !state
.serialized
)
138 pc
= execute_insn(this, pc
, fetch
);
139 bool serialize_before
= (pc
== PC_SERIALIZE_BEFORE
);
143 if (unlikely(state
.single_step
== state
.STEP_STEPPED
) && !serialize_before
) {
144 state
.single_step
= state
.STEP_NONE
;
145 enter_debug_mode(DCSR_CAUSE_STEP
);
146 // enter_debug_mode changed state.pc, so we can't just continue.
150 if (unlikely(state
.pc
>= DEBUG_ROM_ENTRY
&&
151 state
.pc
< DEBUG_END
)) {
152 // We're waiting for the debugger to tell us something.
158 else while (instret
< n
)
160 // This code uses a modified Duff's Device to improve the performance
161 // of executing instructions. While typical Duff's Devices are used
162 // for software pipelining, the switch statement below primarily
163 // benefits from separate call points for the fetch.func function call
164 // found in each execute_insn. This function call is an indirect jump
165 // that depends on the current instruction. By having an indirect jump
166 // dedicated for each icache entry, you improve the performance of the
167 // host's next address predictor. Each case in the switch statement
168 // allows for the program flow to contine to the next case if it
169 // corresponds to the next instruction in the program and instret is
170 // still less than n.
172 // According to Andrew Waterman's recollection, this optimization
173 // resulted in approximately a 2x performance increase.
175 // If there is support for compressed instructions, the mmu and the
176 // switch statement get more complicated. Each branch target is stored
177 // in the index corresponding to mmu->icache_index(), but consecutive
178 // non-branching instructions are stored in consecutive indices even if
179 // mmu->icache_index() specifies a different index (which is the case
180 // for 32-bit instructions in the presence of compressed instructions).
182 // This figures out where to jump to in the switch statement
183 size_t idx
= _mmu
->icache_index(pc
);
185 // This gets the cached decoded instruction from the MMU. If the MMU
186 // does not have the current pc cached, it will refill the MMU and
187 // return the correct entry. ic_entry->data.func is the C++ function
188 // corresponding to the instruction.
189 auto ic_entry
= _mmu
->access_icache(pc
);
191 // This macro is included in "icache.h" included within the switch
192 // statement below. The indirect jump corresponding to the instruction
193 // is located within the execute_insn() function call.
194 #define ICACHE_ACCESS(i) { \
195 insn_fetch_t fetch = ic_entry->data; \
197 pc = execute_insn(this, pc, fetch); \
198 if (i == mmu_t::ICACHE_ENTRIES-1) break; \
199 if (unlikely(ic_entry->tag != pc)) goto miss; \
200 if (unlikely(instret+1 == n)) break; \
205 // This switch statement implements the modified Duff's device as
208 // "icache.h" is generated by the gen_icache script
217 // refill I$ if it looks like there wasn't a taken branch
218 if (pc
> (ic_entry
-1)->tag
&& pc
<= (ic_entry
-1)->tag
+ MAX_INSN_LENGTH
)
219 _mmu
->refill_icache(pc
, ic_entry
);
227 if (unlikely(state
.single_step
== state
.STEP_STEPPED
)) {
228 state
.single_step
= state
.STEP_NONE
;
229 enter_debug_mode(DCSR_CAUSE_STEP
);
232 catch (trigger_matched_t
& t
)
234 if (mmu
->matched_trigger
) {
235 // This exception came from the MMU. That means the instruction hasn't
236 // fully executed yet. We start it again, but this time it won't throw
237 // an exception because matched_trigger is already set. (All memory
238 // instructions are idempotent so restarting is safe.)
240 insn_fetch_t fetch
= mmu
->load_insn(pc
);
241 pc
= execute_insn(this, pc
, fetch
);
244 delete mmu
->matched_trigger
;
245 mmu
->matched_trigger
= NULL
;
247 switch (state
.mcontrol
[t
.index
].action
) {
248 case ACTION_DEBUG_MODE
:
249 enter_debug_mode(DCSR_CAUSE_HWBP
);
251 case ACTION_DEBUG_EXCEPTION
: {
252 mem_trap_t
trap(CAUSE_BREAKPOINT
, t
.address
);
261 state
.minstret
+= instret
;