1 // See LICENSE for license details.
9 static void commit_log_stash_privilege(processor_t
* p
)
11 #ifdef RISCV_ENABLE_COMMITLOG
12 state_t
* state
= p
->get_state();
13 state
->last_inst_priv
= state
->prv
;
14 state
->last_inst_xlen
= p
->get_xlen();
15 state
->last_inst_flen
= p
->get_flen();
19 static void commit_log_print_value(int width
, uint64_t hi
, uint64_t lo
)
23 fprintf(stderr
, "0x%04" PRIx16
, (uint16_t)lo
);
26 fprintf(stderr
, "0x%08" PRIx32
, (uint32_t)lo
);
29 fprintf(stderr
, "0x%016" PRIx64
, lo
);
32 fprintf(stderr
, "0x%016" PRIx64
"%016" PRIx64
, hi
, lo
);
39 static void commit_log_print_insn(state_t
* state
, reg_t pc
, insn_t insn
)
41 #ifdef RISCV_ENABLE_COMMITLOG
42 auto& reg
= state
->log_reg_write
;
43 int priv
= state
->last_inst_priv
;
44 int xlen
= state
->last_inst_xlen
;
45 int flen
= state
->last_inst_flen
;
47 bool fp
= reg
.addr
& 1;
48 int rd
= reg
.addr
>> 1;
49 int size
= fp
? flen
: xlen
;
51 fprintf(stderr
, "%1d ", priv
);
52 commit_log_print_value(xlen
, 0, pc
);
53 fprintf(stderr
, " (");
54 commit_log_print_value(insn
.length() * 8, 0, insn
.bits());
55 fprintf(stderr
, ") %c%2d ", fp
? 'f' : 'x', rd
);
56 commit_log_print_value(size
, reg
.data
.v
[1], reg
.data
.v
[0]);
57 fprintf(stderr
, "\n");
63 inline void processor_t::update_histogram(reg_t pc
)
65 #ifdef RISCV_ENABLE_HISTOGRAM
70 // This is expected to be inlined by the compiler so each use of execute_insn
71 // includes a duplicated body of the function to get separate fetch.func
73 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
75 commit_log_stash_privilege(p
);
76 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
77 if (!invalid_pc(npc
)) {
78 commit_log_print_insn(p
->get_state(), pc
, fetch
.insn
);
79 p
->update_histogram(pc
);
84 bool processor_t::slow_path()
86 return debug
|| state
.single_step
!= state
.STEP_NONE
|| state
.dcsr
.cause
;
89 // fetch/decode/execute loop
90 void processor_t::step(size_t n
)
92 if (state
.dcsr
.cause
== DCSR_CAUSE_NONE
) {
94 enter_debug_mode(DCSR_CAUSE_DEBUGINT
);
95 } // !!!The halt bit in DCSR is deprecated.
96 else if (state
.dcsr
.halt
) {
97 enter_debug_mode(DCSR_CAUSE_HALT
);
106 #define advance_pc() \
107 if (unlikely(invalid_pc(pc))) { \
109 case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
110 case PC_SERIALIZE_AFTER: n = ++instret; break; \
122 take_pending_interrupt();
124 if (unlikely(slow_path()))
128 if (unlikely(state
.single_step
== state
.STEP_STEPPING
)) {
129 state
.single_step
= state
.STEP_STEPPED
;
132 insn_fetch_t fetch
= mmu
->load_insn(pc
);
133 if (debug
&& !state
.serialized
)
135 pc
= execute_insn(this, pc
, fetch
);
136 bool serialize_before
= (pc
== PC_SERIALIZE_BEFORE
);
140 if (unlikely(state
.single_step
== state
.STEP_STEPPED
) && !serialize_before
) {
141 state
.single_step
= state
.STEP_NONE
;
142 enter_debug_mode(DCSR_CAUSE_STEP
);
143 // enter_debug_mode changed state.pc, so we can't just continue.
147 if (unlikely(state
.pc
>= DEBUG_START
&&
148 state
.pc
< DEBUG_END
)) {
149 // We're waiting for the debugger to tell us something.
157 else while (instret
< n
)
159 // This code uses a modified Duff's Device to improve the performance
160 // of executing instructions. While typical Duff's Devices are used
161 // for software pipelining, the switch statement below primarily
162 // benefits from separate call points for the fetch.func function call
163 // found in each execute_insn. This function call is an indirect jump
164 // that depends on the current instruction. By having an indirect jump
165 // dedicated for each icache entry, you improve the performance of the
166 // host's next address predictor. Each case in the switch statement
167 // allows for the program flow to contine to the next case if it
168 // corresponds to the next instruction in the program and instret is
169 // still less than n.
171 // According to Andrew Waterman's recollection, this optimization
172 // resulted in approximately a 2x performance increase.
174 // If there is support for compressed instructions, the mmu and the
175 // switch statement get more complicated. Each branch target is stored
176 // in the index corresponding to mmu->icache_index(), but consecutive
177 // non-branching instructions are stored in consecutive indices even if
178 // mmu->icache_index() specifies a different index (which is the case
179 // for 32-bit instructions in the presence of compressed instructions).
181 // This figures out where to jump to in the switch statement
182 size_t idx
= _mmu
->icache_index(pc
);
184 // This gets the cached decoded instruction from the MMU. If the MMU
185 // does not have the current pc cached, it will refill the MMU and
186 // return the correct entry. ic_entry->data.func is the C++ function
187 // corresponding to the instruction.
188 auto ic_entry
= _mmu
->access_icache(pc
);
190 // This macro is included in "icache.h" included within the switch
191 // statement below. The indirect jump corresponding to the instruction
192 // is located within the execute_insn() function call.
193 #define ICACHE_ACCESS(i) { \
194 insn_fetch_t fetch = ic_entry->data; \
196 pc = execute_insn(this, pc, fetch); \
197 if (i == mmu_t::ICACHE_ENTRIES-1) break; \
198 if (unlikely(ic_entry->tag != pc)) goto miss; \
199 if (unlikely(instret+1 == n)) break; \
204 // This switch statement implements the modified Duff's device as
207 // "icache.h" is generated by the gen_icache script
216 // refill I$ if it looks like there wasn't a taken branch
217 if (pc
> (ic_entry
-1)->tag
&& pc
<= (ic_entry
-1)->tag
+ MAX_INSN_LENGTH
)
218 _mmu
->refill_icache(pc
, ic_entry
);
226 if (unlikely(state
.single_step
== state
.STEP_STEPPED
)) {
227 state
.single_step
= state
.STEP_NONE
;
228 enter_debug_mode(DCSR_CAUSE_STEP
);
231 catch (trigger_matched_t
& t
)
233 if (mmu
->matched_trigger
) {
234 // This exception came from the MMU. That means the instruction hasn't
235 // fully executed yet. We start it again, but this time it won't throw
236 // an exception because matched_trigger is already set. (All memory
237 // instructions are idempotent so restarting is safe.)
239 insn_fetch_t fetch
= mmu
->load_insn(pc
);
240 pc
= execute_insn(this, pc
, fetch
);
243 delete mmu
->matched_trigger
;
244 mmu
->matched_trigger
= NULL
;
246 switch (state
.mcontrol
[t
.index
].action
) {
247 case ACTION_DEBUG_MODE
:
248 enter_debug_mode(DCSR_CAUSE_HWBP
);
250 case ACTION_DEBUG_EXCEPTION
: {
251 mem_trap_t
trap(CAUSE_BREAKPOINT
, t
.address
);
260 state
.minstret
+= instret
;