riscv/gdbserver.cc

   1 #include <arpa/inet.h>
   2 #include <errno.h>
   3 #include <fcntl.h>
   4 #include <stdlib.h>
   5 #include <string.h>
   6 #include <sys/socket.h>
   7 #include <sys/types.h>
   8 #include <unistd.h>
   9
  10 #include <algorithm>
  11 #include <cassert>
  12 #include <cstdio>
  13 #include <vector>
  14
  15 #include "disasm.h"
  16 #include "sim.h"
  17 #include "gdbserver.h"
  18 #include "mmu.h"
  19
  20 #define C_EBREAK        0x9002
  21 #define EBREAK          0x00100073
  22
  23 //////////////////////////////////////// Utility Functions
  24
  25 #undef DEBUG
  26 #ifdef DEBUG
  27 #  define D(x) x
  28 #else
  29 #  define D(x)
  30 #endif // DEBUG
  31
  32 void die(const char* msg)
  33 {
  34   fprintf(stderr, "gdbserver code died: %s\n", msg);
  35   abort();
  36 }
  37
  38 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
  39 // its source tree. We must interpret the numbers the same here.
  40 enum {
  41   REG_XPR0 = 0,
  42   REG_XPR31 = 31,
  43   REG_PC = 32,
  44   REG_FPR0 = 33,
  45   REG_FPR31 = 64,
  46   REG_CSR0 = 65,
  47   REG_CSR4095 = 4160,
  48   REG_PRIV = 4161
  49 };
  50
  51 //////////////////////////////////////// Functions to generate RISC-V opcodes.
  52
  53 // TODO: Does this already exist somewhere?
  54
  55 #define ZERO    0
  56 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
  57 // spec says it should be 2 and 3.
  58 #define S0      8
  59 #define S1      9
  60 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
  61   return (value >> lo) & ((1 << (hi+1-lo)) - 1);
  62 }
  63
  64 static uint32_t bit(uint32_t value, unsigned int b) {
  65   return (value >> b) & 1;
  66 }
  67
  68 static uint32_t jal(unsigned int rd, uint32_t imm) {
  69   return (bit(imm, 20) << 31) |
  70     (bits(imm, 10, 1) << 21) |
  71     (bit(imm, 11) << 20) |
  72     (bits(imm, 19, 12) << 12) |
  73     (rd << 7) |
  74     MATCH_JAL;
  75 }
  76
  77 static uint32_t csrsi(unsigned int csr, uint16_t imm) {
  78   return (csr << 20) |
  79     (bits(imm, 4, 0) << 15) |
  80     MATCH_CSRRSI;
  81 }
  82
  83 static uint32_t csrci(unsigned int csr, uint16_t imm) {
  84   return (csr << 20) |
  85     (bits(imm, 4, 0) << 15) |
  86     MATCH_CSRRCI;
  87 }
  88
  89 static uint32_t csrr(unsigned int rd, unsigned int csr) {
  90   return (csr << 20) | (rd << 7) | MATCH_CSRRS;
  91 }
  92
  93 static uint32_t csrw(unsigned int source, unsigned int csr) {
  94   return (csr << 20) | (source << 15) | MATCH_CSRRW;
  95 }
  96
  97 static uint32_t fence_i()
  98 {
  99   return MATCH_FENCE_I;
 100 }
 101
 102 static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
 103 {
 104   return (bits(offset, 11, 5) << 25) |
 105     (src << 20) |
 106     (base << 15) |
 107     (bits(offset, 4, 0) << 7) |
 108     MATCH_SB;
 109 }
 110
 111 static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
 112 {
 113   return (bits(offset, 11, 5) << 25) |
 114     (src << 20) |
 115     (base << 15) |
 116     (bits(offset, 4, 0) << 7) |
 117     MATCH_SH;
 118 }
 119
 120 static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
 121 {
 122   return (bits(offset, 11, 5) << 25) |
 123     (src << 20) |
 124     (base << 15) |
 125     (bits(offset, 4, 0) << 7) |
 126     MATCH_SW;
 127 }
 128
 129 static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
 130 {
 131   return (bits(offset, 11, 5) << 25) |
 132     (bits(src, 4, 0) << 20) |
 133     (base << 15) |
 134     (bits(offset, 4, 0) << 7) |
 135     MATCH_SD;
 136 }
 137
 138 static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
 139 {
 140 #if 0
 141   return (bits(offset, 11, 5) << 25) |
 142     (bits(src, 4, 0) << 20) |
 143     (base << 15) |
 144     (bits(offset, 4, 0) << 7) |
 145     MATCH_SQ;
 146 #else
 147   abort();
 148 #endif
 149 }
 150
 151 static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
 152 {
 153 #if 0
 154   return (bits(offset, 11, 0) << 20) |
 155     (base << 15) |
 156     (bits(rd, 4, 0) << 7) |
 157     MATCH_LQ;
 158 #else
 159   abort();
 160 #endif
 161 }
 162
 163 static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
 164 {
 165   return (bits(offset, 11, 0) << 20) |
 166     (base << 15) |
 167     (bits(rd, 4, 0) << 7) |
 168     MATCH_LD;
 169 }
 170
 171 static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
 172 {
 173   return (bits(offset, 11, 0) << 20) |
 174     (base << 15) |
 175     (bits(rd, 4, 0) << 7) |
 176     MATCH_LW;
 177 }
 178
 179 static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
 180 {
 181   return (bits(offset, 11, 0) << 20) |
 182     (base << 15) |
 183     (bits(rd, 4, 0) << 7) |
 184     MATCH_LH;
 185 }
 186
 187 static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
 188 {
 189   return (bits(offset, 11, 0) << 20) |
 190     (base << 15) |
 191     (bits(rd, 4, 0) << 7) |
 192     MATCH_LB;
 193 }
 194
 195 static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
 196 {
 197   return (bits(offset, 11, 5) << 25) |
 198     (bits(src, 4, 0) << 20) |
 199     (base << 15) |
 200     (bits(offset, 4, 0) << 7) |
 201     MATCH_FSW;
 202 }
 203
 204 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
 205 {
 206   return (bits(offset, 11, 5) << 25) |
 207     (bits(src, 4, 0) << 20) |
 208     (base << 15) |
 209     (bits(offset, 4, 0) << 7) |
 210     MATCH_FSD;
 211 }
 212
 213 static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
 214 {
 215   return (bits(offset, 11, 5) << 25) |
 216     (bits(src, 4, 0) << 20) |
 217     (base << 15) |
 218     (bits(offset, 4, 0) << 7) |
 219     MATCH_FLW;
 220 }
 221
 222 static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
 223 {
 224   return (bits(offset, 11, 5) << 25) |
 225     (bits(src, 4, 0) << 20) |
 226     (base << 15) |
 227     (bits(offset, 4, 0) << 7) |
 228     MATCH_FLD;
 229 }
 230
 231 static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
 232 {
 233   return (bits(imm, 11, 0) << 20) |
 234     (src << 15) |
 235     (dest << 7) |
 236     MATCH_ADDI;
 237 }
 238
 239 static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
 240 {
 241   return (bits(imm, 11, 0) << 20) |
 242     (src << 15) |
 243     (dest << 7) |
 244     MATCH_ORI;
 245 }
 246
 247 static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
 248 {
 249   return (bits(imm, 11, 0) << 20) |
 250     (src << 15) |
 251     (dest << 7) |
 252     MATCH_XORI;
 253 }
 254
 255 static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
 256 {
 257   return (bits(shamt, 4, 0) << 20) |
 258     (src << 15) |
 259     (dest << 7) |
 260     MATCH_SRLI;
 261 }
 262
 263
 264 static uint32_t nop()
 265 {
 266   return addi(0, 0, 0);
 267 }
 268
 269 template <typename T>
 270 unsigned int circular_buffer_t<T>::size() const
 271 {
 272   if (end >= start)
 273     return end - start;
 274   else
 275     return end + capacity - start;
 276 }
 277
 278 template <typename T>
 279 void circular_buffer_t<T>::consume(unsigned int bytes)
 280 {
 281   start = (start + bytes) % capacity;
 282 }
 283
 284 template <typename T>
 285 unsigned int circular_buffer_t<T>::contiguous_empty_size() const
 286 {
 287   if (end >= start)
 288     if (start == 0)
 289       return capacity - end - 1;
 290     else
 291       return capacity - end;
 292   else
 293     return start - end - 1;
 294 }
 295
 296 template <typename T>
 297 unsigned int circular_buffer_t<T>::contiguous_data_size() const
 298 {
 299   if (end >= start)
 300     return end - start;
 301   else
 302     return capacity - start;
 303 }
 304
 305 template <typename T>
 306 void circular_buffer_t<T>::data_added(unsigned int bytes)
 307 {
 308   end += bytes;
 309   assert(end <= capacity);
 310   if (end == capacity)
 311     end = 0;
 312 }
 313
 314 template <typename T>
 315 void circular_buffer_t<T>::reset()
 316 {
 317   start = 0;
 318   end = 0;
 319 }
 320
 321 template <typename T>
 322 void circular_buffer_t<T>::append(const T *src, unsigned int count)
 323 {
 324   unsigned int copy = std::min(count, contiguous_empty_size());
 325   memcpy(contiguous_empty(), src, copy * sizeof(T));
 326   data_added(copy);
 327   count -= copy;
 328   if (count > 0) {
 329     assert(count < contiguous_empty_size());
 330     memcpy(contiguous_empty(), src, count * sizeof(T));
 331     data_added(count);
 332   }
 333 }
 334
 335 ////////////////////////////// Debug Operations
 336
 337 class halt_op_t : public operation_t
 338 {
 339   public:
 340     halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
 341       operation_t(gdbserver), send_status(send_status),
 342       state(ST_ENTER) {};
 343
 344     void write_dpc_program() {
 345       gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
 346       gs.dr_write32(1, csrr(S0, CSR_DPC));
 347       gs.dr_write_store(2, S0, SLOT_DATA0);
 348       gs.dr_write_jump(3);
 349       gs.set_interrupt(0);
 350     }
 351
 352     bool perform_step(unsigned int step) {
 353       switch (state) {
 354         gs.tselect_valid = false;
 355         case ST_ENTER:
 356           if (gs.xlen == 0) {
 357             gs.dr_write32(0, xori(S1, ZERO, -1));
 358             gs.dr_write32(1, srli(S1, S1, 31));
 359             // 0x00000001  0x00000001:ffffffff  0x00000001:ffffffff:ffffffff:ffffffff
 360             gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
 361             gs.dr_write32(3, srli(S1, S1, 31));
 362             // 0x00000000  0x00000000:00000003  0x00000000:00000003:ffffffff:ffffffff
 363             gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
 364             gs.dr_write_jump(5);
 365             gs.set_interrupt(0);
 366             state = ST_XLEN;
 367
 368           } else {
 369             write_dpc_program();
 370             state = ST_DPC;
 371           }
 372           return false;
 373
 374         case ST_XLEN:
 375           {
 376             uint32_t word0 = gs.dr_read32(0);
 377             uint32_t word1 = gs.dr_read32(1);
 378
 379             if (word0 == 1 && word1 == 0) {
 380               gs.xlen = 32;
 381             } else if (word0 == 0xffffffff && word1 == 3) {
 382               gs.xlen = 64;
 383             } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
 384               gs.xlen = 128;
 385             }
 386
 387             write_dpc_program();
 388             state = ST_DPC;
 389             return false;
 390           }
 391
 392         case ST_DPC:
 393           gs.dpc = gs.dr_read(SLOT_DATA0);
 394           gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
 395           gs.dr_write_store(1, S0, SLOT_DATA0);
 396           gs.dr_write_jump(2);
 397           gs.set_interrupt(0);
 398           state = ST_MSTATUS;
 399           return false;
 400
 401         case ST_MSTATUS:
 402           gs.mstatus = gs.dr_read(SLOT_DATA0);
 403           gs.dr_write32(0, csrr(S0, CSR_DCSR));
 404           gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 405           gs.dr_write_jump(2);
 406           gs.set_interrupt(0);
 407           state = ST_DCSR;
 408           return false;
 409
 410         case ST_DCSR:
 411           gs.dcsr = gs.dr_read32(4);
 412
 413           gs.sptbr_valid = false;
 414           gs.pte_cache.clear();
 415
 416           if (send_status) {
 417             switch (get_field(gs.dcsr, DCSR_CAUSE)) {
 418               case DCSR_CAUSE_NONE:
 419                 fprintf(stderr, "Internal error. Processor halted without reason.\n");
 420                 abort();
 421
 422               case DCSR_CAUSE_DEBUGINT:
 423                 gs.send_packet("S02");   // Pretend program received SIGINT.
 424                 break;
 425
 426               case DCSR_CAUSE_HWBP:
 427               case DCSR_CAUSE_STEP:
 428               case DCSR_CAUSE_HALT:
 429                 // There's no gdb code for this.
 430                 gs.send_packet("T05");
 431                 break;
 432               case DCSR_CAUSE_SWBP:
 433                 gs.send_packet("T05swbreak:;");
 434                 break;
 435             }
 436           }
 437           return true;
 438
 439         default:
 440           assert(0);
 441       }
 442     }
 443
 444   private:
 445     bool send_status;
 446     enum {
 447       ST_ENTER,
 448       ST_XLEN,
 449       ST_DPC,
 450       ST_MSTATUS,
 451       ST_DCSR
 452     } state;
 453 };
 454
 455 class continue_op_t : public operation_t
 456 {
 457   public:
 458     continue_op_t(gdbserver_t& gdbserver, bool single_step) :
 459       operation_t(gdbserver), single_step(single_step) {};
 460
 461     bool perform_step(unsigned int step) {
 462       switch (step) {
 463         case 0:
 464           gs.dr_write_load(0, S0, SLOT_DATA0);
 465           gs.dr_write32(1, csrw(S0, CSR_DPC));
 466           // TODO: Isn't there a fence.i in Debug ROM already?
 467           if (gs.fence_i_required) {
 468             gs.dr_write32(2, fence_i());
 469             gs.dr_write_jump(3);
 470             gs.fence_i_required = false;
 471           } else {
 472             gs.dr_write_jump(2);
 473           }
 474           gs.dr_write(SLOT_DATA0, gs.dpc);
 475           gs.set_interrupt(0);
 476           return false;
 477
 478         case 1:
 479           gs.dr_write_load(0, S0, SLOT_DATA0);
 480           gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
 481           gs.dr_write_jump(2);
 482           gs.dr_write(SLOT_DATA0, gs.mstatus);
 483           gs.set_interrupt(0);
 484           return false;
 485
 486         case 2:
 487           gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
 488           gs.dr_write32(1, csrw(S0, CSR_DCSR));
 489           gs.dr_write_jump(2);
 490
 491           reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
 492           dcsr = set_field(dcsr, DCSR_STEP, single_step);
 493           // Software breakpoints should go here.
 494           dcsr = set_field(dcsr, DCSR_EBREAKM, 1);
 495           dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
 496           dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
 497           dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
 498           gs.dr_write32(4, dcsr);
 499
 500           gs.set_interrupt(0);
 501           return true;
 502       }
 503       return false;
 504     }
 505
 506   private:
 507     bool single_step;
 508 };
 509
 510 class general_registers_read_op_t : public operation_t
 511 {
 512   // Register order that gdb expects is:
 513   //   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
 514   //   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
 515   //   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
 516   //   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
 517
 518   // Each byte of register data is described by two hex digits. The bytes with
 519   // the register are transmitted in target byte order. The size of each
 520   // register and their position within the ‘g’ packet are determined by the
 521   // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
 522   // gdbarch_register_name.
 523
 524   public:
 525     general_registers_read_op_t(gdbserver_t& gdbserver) :
 526       operation_t(gdbserver) {};
 527
 528     bool perform_step(unsigned int step)
 529     {
 530       D(fprintf(stderr, "register_read step %d\n", step));
 531       if (step == 0) {
 532         gs.start_packet();
 533
 534         // x0 is always zero.
 535         if (gs.xlen == 32) {
 536           gs.send((uint32_t) 0);
 537         } else {
 538           gs.send((uint64_t) 0);
 539         }
 540
 541         gs.dr_write_store(0, 1, SLOT_DATA0);
 542         gs.dr_write_store(1, 2, SLOT_DATA1);
 543         gs.dr_write_jump(2);
 544         gs.set_interrupt(0);
 545         return false;
 546       }
 547
 548       if (gs.xlen == 32) {
 549         gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
 550       } else {
 551         gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
 552       }
 553       if (step >= 16) {
 554         gs.end_packet();
 555         return true;
 556       }
 557
 558       if (gs.xlen == 32) {
 559         gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
 560       } else {
 561         gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
 562       }
 563
 564       unsigned int current_reg = 2 * step + 1;
 565       unsigned int i = 0;
 566       if (current_reg == S1) {
 567         gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
 568       }
 569       gs.dr_write_store(i++, current_reg, SLOT_DATA0);
 570       if (current_reg + 1 == S0) {
 571         gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
 572       }
 573       if (step < 15) {
 574         gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
 575       }
 576       gs.dr_write_jump(i);
 577       gs.set_interrupt(0);
 578
 579       return false;
 580     }
 581 };
 582
 583 class register_read_op_t : public operation_t
 584 {
 585   public:
 586     register_read_op_t(gdbserver_t& gdbserver, unsigned int reg) :
 587       operation_t(gdbserver), reg(reg) {};
 588
 589     bool perform_step(unsigned int step)
 590     {
 591       switch (step) {
 592         case 0:
 593           if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 594             die("handle_register_read");
 595             // send(p->state.XPR[reg - REG_XPR0]);
 596           } else if (reg == REG_PC) {
 597             gs.start_packet();
 598             if (gs.xlen == 32) {
 599               gs.send((uint32_t) gs.dpc);
 600             } else {
 601               gs.send(gs.dpc);
 602             }
 603             gs.end_packet();
 604             return true;
 605           } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 606             // send(p->state.FPR[reg - REG_FPR0]);
 607             if (gs.xlen == 32) {
 608               gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 609             } else {
 610               gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 611             }
 612             gs.dr_write_jump(1);
 613           } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 614             gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
 615             gs.dr_write_store(1, S0, SLOT_DATA0);
 616             gs.dr_write_jump(2);
 617             // If we hit an exception reading the CSR, we'll end up returning ~0 as
 618             // the register's value, which is what we want. (Right?)
 619             gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
 620           } else if (reg == REG_PRIV) {
 621             gs.start_packet();
 622             gs.send((uint8_t) get_field(gs.dcsr, DCSR_PRV));
 623             gs.end_packet();
 624             return true;
 625           } else {
 626             gs.send_packet("E02");
 627             return true;
 628           }
 629           gs.set_interrupt(0);
 630           return false;
 631
 632         case 1:
 633           gs.start_packet();
 634           if (gs.xlen == 32) {
 635             gs.send(gs.dr_read32(4));
 636           } else {
 637             gs.send(gs.dr_read(SLOT_DATA0));
 638           }
 639           gs.end_packet();
 640           return true;
 641       }
 642       return false;
 643     }
 644
 645   private:
 646     unsigned int reg;
 647 };
 648
 649 class register_write_op_t : public operation_t
 650 {
 651   public:
 652     register_write_op_t(gdbserver_t& gdbserver, unsigned int reg, reg_t value) :
 653       operation_t(gdbserver), reg(reg), value(value) {};
 654
 655     bool perform_step(unsigned int step)
 656     {
 657       gs.dr_write_load(0, S0, SLOT_DATA0);
 658       gs.dr_write(SLOT_DATA0, value);
 659       if (reg == S0) {
 660         gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
 661         gs.dr_write_jump(2);
 662       } else if (reg == S1) {
 663         gs.dr_write_store(1, S0, SLOT_DATA_LAST);
 664         gs.dr_write_jump(2);
 665       } else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 666         gs.dr_write32(1, addi(reg, S0, 0));
 667         gs.dr_write_jump(2);
 668       } else if (reg == REG_PC) {
 669         gs.dpc = value;
 670         return true;
 671       } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 672         if (gs.xlen == 32) {
 673           gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 674         } else {
 675           gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 676         }
 677         gs.dr_write_jump(1);
 678       } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 679         gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
 680         gs.dr_write_jump(2);
 681         if (reg == REG_CSR0 + CSR_SPTBR) {
 682           gs.sptbr = value;
 683           gs.sptbr_valid = true;
 684         }
 685       } else if (reg == REG_PRIV) {
 686         gs.dcsr = set_field(gs.dcsr, DCSR_PRV, value);
 687         return true;
 688       } else {
 689         gs.send_packet("E02");
 690         return true;
 691       }
 692       gs.set_interrupt(0);
 693       gs.send_packet("OK");
 694       return true;
 695     }
 696
 697   private:
 698     unsigned int reg;
 699     reg_t value;
 700 };
 701
 702 class memory_read_op_t : public operation_t
 703 {
 704   public:
 705     // Read length bytes from vaddr, storing the result into data.
 706     // If data is NULL, send the result straight to gdb.
 707     memory_read_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 708         unsigned char *data=NULL) :
 709       operation_t(gdbserver), vaddr(vaddr), length(length), data(data) {};
 710
 711     bool perform_step(unsigned int step)
 712     {
 713       if (step == 0) {
 714         // address goes in S0
 715         paddr = gs.translate(vaddr);
 716         access_size = gs.find_access_size(paddr, length);
 717
 718         gs.dr_write_load(0, S0, SLOT_DATA0);
 719         switch (access_size) {
 720           case 1:
 721             gs.dr_write32(1, lb(S1, S0, 0));
 722             break;
 723           case 2:
 724             gs.dr_write32(1, lh(S1, S0, 0));
 725             break;
 726           case 4:
 727             gs.dr_write32(1, lw(S1, S0, 0));
 728             break;
 729           case 8:
 730             gs.dr_write32(1, ld(S1, S0, 0));
 731             break;
 732         }
 733         gs.dr_write_store(2, S1, SLOT_DATA1);
 734         gs.dr_write_jump(3);
 735         gs.dr_write(SLOT_DATA0, paddr);
 736         gs.set_interrupt(0);
 737
 738         if (!data) {
 739           gs.start_packet();
 740         }
 741         return false;
 742       }
 743
 744       char buffer[3];
 745       reg_t value = gs.dr_read(SLOT_DATA1);
 746       for (unsigned int i = 0; i < access_size; i++) {
 747         if (data) {
 748           *(data++) = value & 0xff;
 749           D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
 750         } else {
 751           sprintf(buffer, "%02x", (unsigned int) (value & 0xff));
 752           gs.send(buffer);
 753         }
 754         value >>= 8;
 755       }
 756       if (data) {
 757         D(fprintf(stderr, "\n"));
 758       }
 759       length -= access_size;
 760       paddr += access_size;
 761
 762       if (length == 0) {
 763         if (!data) {
 764           gs.end_packet();
 765         }
 766         return true;
 767       } else {
 768         gs.dr_write(SLOT_DATA0, paddr);
 769         gs.set_interrupt(0);
 770         return false;
 771       }
 772     }
 773
 774   private:
 775     reg_t vaddr;
 776     unsigned int length;
 777     unsigned char* data;
 778     reg_t paddr;
 779     unsigned int access_size;
 780 };
 781
 782 class memory_write_op_t : public operation_t
 783 {
 784   public:
 785     memory_write_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 786         const unsigned char *data) :
 787       operation_t(gdbserver), vaddr(vaddr), offset(0), length(length), data(data) {};
 788
 789     ~memory_write_op_t() {
 790       delete[] data;
 791     }
 792
 793     bool perform_step(unsigned int step)
 794     {
 795       reg_t paddr = gs.translate(vaddr);
 796
 797       unsigned int data_offset;
 798       switch (gs.xlen) {
 799         case 32:
 800           data_offset = slot_offset32[SLOT_DATA1];
 801           break;
 802         case 64:
 803           data_offset = slot_offset64[SLOT_DATA1];
 804           break;
 805         case 128:
 806           data_offset = slot_offset128[SLOT_DATA1];
 807           break;
 808         default:
 809           abort();
 810       }
 811
 812       if (step == 0) {
 813         access_size = gs.find_access_size(paddr, length);
 814
 815         D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
 816             access_size));
 817         for (unsigned int i = 0; i < length; i++) {
 818           D(fprintf(stderr, "%02x", data[i]));
 819         }
 820         D(fprintf(stderr, "\n"));
 821
 822         // address goes in S0
 823         gs.dr_write_load(0, S0, SLOT_DATA0);
 824         switch (access_size) {
 825           case 1:
 826             gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 827             gs.dr_write32(2, sb(S1, S0, 0));
 828             gs.dr_write32(data_offset, data[0]);
 829             break;
 830           case 2:
 831             gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 832             gs.dr_write32(2, sh(S1, S0, 0));
 833             gs.dr_write32(data_offset, data[0] | (data[1] << 8));
 834             break;
 835           case 4:
 836             gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 837             gs.dr_write32(2, sw(S1, S0, 0));
 838             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 839                 (data[2] << 16) | (data[3] << 24));
 840             break;
 841           case 8:
 842             gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 843             gs.dr_write32(2, sd(S1, S0, 0));
 844             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 845                 (data[2] << 16) | (data[3] << 24));
 846             gs.dr_write32(data_offset+1, data[4] | (data[5] << 8) |
 847                 (data[6] << 16) | (data[7] << 24));
 848             break;
 849           default:
 850             fprintf(stderr, "gdbserver error: write %d bytes to 0x%lx -> 0x%lx; "
 851                 "access_size=%d\n", length, vaddr, paddr, access_size);
 852             gs.send_packet("E12");
 853             return true;
 854         }
 855         gs.dr_write_jump(3);
 856         gs.dr_write(SLOT_DATA0, paddr);
 857         gs.set_interrupt(0);
 858
 859         return false;
 860       }
 861
 862       if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
 863         fprintf(stderr, "Exception happened while writing to 0x%lx -> 0x%lx\n",
 864             vaddr, paddr);
 865       }
 866
 867       offset += access_size;
 868       if (offset >= length) {
 869         gs.send_packet("OK");
 870         return true;
 871       } else {
 872         const unsigned char *d = data + offset;
 873         switch (access_size) {
 874           case 1:
 875             gs.dr_write32(data_offset, d[0]);
 876             break;
 877           case 2:
 878             gs.dr_write32(data_offset, d[0] | (d[1] << 8));
 879             break;
 880           case 4:
 881             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 882                 (d[2] << 16) | (d[3] << 24));
 883             break;
 884           case 8:
 885             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 886                 (d[2] << 16) | (d[3] << 24));
 887             gs.dr_write32(data_offset+1, d[4] | (d[5] << 8) |
 888                 (d[6] << 16) | (d[7] << 24));
 889             break;
 890           default:
 891             gs.send_packet("E13");
 892             return true;
 893         }
 894         gs.dr_write(SLOT_DATA0, paddr + offset);
 895         gs.set_interrupt(0);
 896         return false;
 897       }
 898     }
 899
 900   private:
 901     reg_t vaddr;
 902     unsigned int offset;
 903     unsigned int length;
 904     unsigned int access_size;
 905     const unsigned char *data;
 906 };
 907
 908 class collect_translation_info_op_t : public operation_t
 909 {
 910   public:
 911     // Read sufficient information from the target into gdbserver structures so
 912     // that it's possible to translate vaddr, vaddr+length, and all addresses
 913     // in between to physical addresses.
 914     collect_translation_info_op_t(gdbserver_t& gdbserver, reg_t vaddr, size_t length) :
 915       operation_t(gdbserver), state(STATE_START), vaddr(vaddr), length(length) {};
 916
 917     bool perform_step(unsigned int step)
 918     {
 919       unsigned int vm = gs.virtual_memory();
 920
 921       if (step == 0) {
 922         switch (vm) {
 923           case VM_MBARE:
 924             // Nothing to be done.
 925             return true;
 926
 927           case VM_SV32:
 928             levels = 2;
 929             ptidxbits = 10;
 930             ptesize = 4;
 931             break;
 932           case VM_SV39:
 933             levels = 3;
 934             ptidxbits = 9;
 935             ptesize = 8;
 936             break;
 937           case VM_SV48:
 938             levels = 4;
 939             ptidxbits = 9;
 940             ptesize = 8;
 941             break;
 942
 943           default:
 944             {
 945               char buf[100];
 946               sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
 947               die(buf);
 948               return true;        // die doesn't return, but gcc doesn't know that.
 949             }
 950         }
 951       }
 952
 953       // Perform any reads from the just-completed action.
 954       switch (state) {
 955         case STATE_START:
 956           break;
 957         case STATE_READ_SPTBR:
 958           gs.sptbr = gs.dr_read(SLOT_DATA0);
 959           gs.sptbr_valid = true;
 960           break;
 961         case STATE_READ_PTE:
 962           if (ptesize == 4) {
 963               gs.pte_cache[pte_addr] = gs.dr_read32(4);
 964           } else {
 965               gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
 966                   gs.dr_read32(4);
 967           }
 968           D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
 969           break;
 970       }
 971
 972       // Set up the next action.
 973       // We only get here for VM_SV32/39/38.
 974
 975       if (!gs.sptbr_valid) {
 976         state = STATE_READ_SPTBR;
 977         gs.dr_write32(0, csrr(S0, CSR_SPTBR));
 978         gs.dr_write_store(1, S0, SLOT_DATA0);
 979         gs.dr_write_jump(2);
 980         gs.set_interrupt(0);
 981         return false;
 982       }
 983
 984       reg_t base = gs.sptbr << PGSHIFT;
 985       int ptshift = (levels - 1) * ptidxbits;
 986       for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 987         reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 988
 989         pte_addr = base + idx * ptesize;
 990         auto it = gs.pte_cache.find(pte_addr);
 991         if (it == gs.pte_cache.end()) {
 992           state = STATE_READ_PTE;
 993           if (ptesize == 4) {
 994             gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 995             gs.dr_write32(1, lw(S1, S0, 0));
 996             gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
 997           } else {
 998             assert(gs.xlen >= 64);
 999             gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
1000             gs.dr_write32(1, ld(S1, S0, 0));
1001             gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1002           }
1003           gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
1004           gs.dr_write32(4, pte_addr);
1005           gs.dr_write32(5, pte_addr >> 32);
1006           gs.set_interrupt(0);
1007           return false;
1008         }
1009
1010         reg_t pte = gs.pte_cache[pte_addr];
1011         reg_t ppn = pte >> PTE_PPN_SHIFT;
1012
1013         if (PTE_TABLE(pte)) { // next level of page table
1014           base = ppn << PGSHIFT;
1015         } else {
1016           // We've collected all the data required for the translation.
1017           return true;
1018         }
1019       }
1020       fprintf(stderr,
1021           "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%lx\n",
1022           vaddr);
1023       return true;
1024     }
1025
1026   private:
1027     enum {
1028       STATE_START,
1029       STATE_READ_SPTBR,
1030       STATE_READ_PTE
1031     } state;
1032     reg_t vaddr;
1033     size_t length;
1034     unsigned int levels;
1035     unsigned int ptidxbits;
1036     unsigned int ptesize;
1037     reg_t pte_addr;
1038 };
1039
1040 class hardware_breakpoint_insert_op_t : public operation_t
1041 {
1042   public:
1043     hardware_breakpoint_insert_op_t(gdbserver_t& gdbserver,
1044         hardware_breakpoint_t bp) :
1045       operation_t(gdbserver), state(STATE_START), bp(bp) {};
1046
1047     void write_new_index_program()
1048     {
1049       gs.dr_write_load(0, S0, SLOT_DATA1);
1050       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1051       gs.dr_write32(2, csrr(S0, CSR_TSELECT));
1052       gs.dr_write_store(3, S0, SLOT_DATA1);
1053       gs.dr_write_jump(4);
1054       gs.dr_write(SLOT_DATA1, bp.index);
1055     }
1056
1057     bool perform_step(unsigned int step)
1058     {
1059       switch (state) {
1060         case STATE_START:
1061           bp.index = 0;
1062           write_new_index_program();
1063           state = STATE_CHECK_INDEX;
1064           break;
1065
1066         case STATE_CHECK_INDEX:
1067           if (gs.dr_read(SLOT_DATA1) != bp.index) {
1068             // We've exhausted breakpoints without finding an appropriate one.
1069             gs.send_packet("E58");
1070             return true;
1071           }
1072
1073           gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1074           gs.dr_write_store(1, S0, SLOT_DATA0);
1075           gs.dr_write_jump(2);
1076           state = STATE_CHECK_MCONTROL;
1077           break;
1078
1079         case STATE_CHECK_MCONTROL:
1080           {
1081             reg_t mcontrol = gs.dr_read(SLOT_DATA0);
1082             unsigned int type = mcontrol >> (gs.xlen - 4);
1083             if (type == 0) {
1084               // We've exhausted breakpoints without finding an appropriate one.
1085               gs.send_packet("E58");
1086               return true;
1087             }
1088
1089             if (type == 2 &&
1090                 !get_field(mcontrol, MCONTROL_EXECUTE) &&
1091                 !get_field(mcontrol, MCONTROL_LOAD) &&
1092                 !get_field(mcontrol, MCONTROL_STORE)) {
1093               // Found an unused trigger.
1094               gs.dr_write_load(0, S0, SLOT_DATA1);
1095               gs.dr_write32(1, csrw(S0, CSR_TDATA1));
1096               gs.dr_write_jump(2);
1097               mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE);
1098               mcontrol = set_field(mcontrol, MCONTROL_DMODE(gs.xlen), 1);
1099               mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
1100               mcontrol = set_field(mcontrol, MCONTROL_M, 1);
1101               mcontrol = set_field(mcontrol, MCONTROL_H, 1);
1102               mcontrol = set_field(mcontrol, MCONTROL_S, 1);
1103               mcontrol = set_field(mcontrol, MCONTROL_U, 1);
1104               mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
1105               mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
1106               mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
1107               gs.dr_write(SLOT_DATA1, mcontrol);
1108               state = STATE_WRITE_ADDRESS;
1109             } else {
1110               bp.index++;
1111               write_new_index_program();
1112               state = STATE_CHECK_INDEX;
1113             }
1114           }
1115           break;
1116
1117         case STATE_WRITE_ADDRESS:
1118           {
1119             gs.dr_write_load(0, S0, SLOT_DATA1);
1120             gs.dr_write32(1, csrw(S0, CSR_TDATA2));
1121             gs.dr_write_jump(2);
1122             gs.dr_write(SLOT_DATA1, bp.vaddr);
1123             gs.set_interrupt(0);
1124             gs.send_packet("OK");
1125
1126             gs.hardware_breakpoints.insert(bp);
1127
1128             return true;
1129           }
1130       }
1131
1132       gs.set_interrupt(0);
1133       return false;
1134     }
1135
1136   private:
1137     enum {
1138       STATE_START,
1139       STATE_CHECK_INDEX,
1140       STATE_CHECK_MCONTROL,
1141       STATE_WRITE_ADDRESS
1142     } state;
1143     hardware_breakpoint_t bp;
1144 };
1145
1146 class maybe_save_tselect_op_t : public operation_t
1147 {
1148   public:
1149     maybe_save_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1150     bool perform_step(unsigned int step) {
1151       if (gs.tselect_valid)
1152         return true;
1153
1154       switch (step) {
1155         case 0:
1156           gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1157           gs.dr_write_store(1, S0, SLOT_DATA0);
1158           gs.dr_write_jump(2);
1159           gs.set_interrupt(0);
1160           return false;
1161         case 1:
1162           gs.tselect = gs.dr_read(SLOT_DATA0);
1163           gs.tselect_valid = true;
1164           break;
1165       }
1166       return true;
1167     }
1168 };
1169
1170 class maybe_restore_tselect_op_t : public operation_t
1171 {
1172   public:
1173     maybe_restore_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1174     bool perform_step(unsigned int step) {
1175       if (gs.tselect_valid) {
1176         gs.dr_write_load(0, S0, SLOT_DATA1);
1177         gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1178         gs.dr_write_jump(2);
1179         gs.dr_write(SLOT_DATA1, gs.tselect);
1180       }
1181       return true;
1182     }
1183 };
1184
1185 class hardware_breakpoint_remove_op_t : public operation_t
1186 {
1187   public:
1188     hardware_breakpoint_remove_op_t(gdbserver_t& gdbserver,
1189         hardware_breakpoint_t bp) :
1190       operation_t(gdbserver), bp(bp) {};
1191
1192     bool perform_step(unsigned int step) {
1193       gs.dr_write32(0, addi(S0, ZERO, bp.index));
1194       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1195       gs.dr_write32(2, csrw(ZERO, CSR_TDATA1));
1196       gs.dr_write_jump(3);
1197       gs.set_interrupt(0);
1198       return true;
1199     }
1200
1201   private:
1202     hardware_breakpoint_t bp;
1203 };
1204
1205 ////////////////////////////// gdbserver itself
1206
1207 gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
1208   xlen(0),
1209   sim(sim),
1210   client_fd(0),
1211   recv_buf(64 * 1024), send_buf(64 * 1024)
1212 {
1213   socket_fd = socket(AF_INET, SOCK_STREAM, 0);
1214   if (socket_fd == -1) {
1215     fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
1216     abort();
1217   }
1218
1219   fcntl(socket_fd, F_SETFL, O_NONBLOCK);
1220   int reuseaddr = 1;
1221   if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
1222         sizeof(int)) == -1) {
1223     fprintf(stderr, "failed setsockopt: %s (%d)\n", strerror(errno), errno);
1224     abort();
1225   }
1226
1227   struct sockaddr_in addr;
1228   memset(&addr, 0, sizeof(addr));
1229   addr.sin_family = AF_INET;
1230   addr.sin_addr.s_addr = INADDR_ANY;
1231   addr.sin_port = htons(port);
1232
1233   if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
1234     fprintf(stderr, "failed to bind socket: %s (%d)\n", strerror(errno), errno);
1235     abort();
1236   }
1237
1238   if (listen(socket_fd, 1) == -1) {
1239     fprintf(stderr, "failed to listen on socket: %s (%d)\n", strerror(errno), errno);
1240     abort();
1241   }
1242 }
1243
1244 unsigned int gdbserver_t::find_access_size(reg_t address, int length)
1245 {
1246   reg_t composite = address | length;
1247   if ((composite & 0x7) == 0 && xlen >= 64)
1248     return 8;
1249   if ((composite & 0x3) == 0)
1250     return 4;
1251   return 1;
1252 }
1253
1254 reg_t gdbserver_t::translate(reg_t vaddr)
1255 {
1256   unsigned int vm = virtual_memory();
1257   unsigned int levels, ptidxbits, ptesize;
1258
1259   switch (vm) {
1260     case VM_MBARE:
1261       return vaddr;
1262
1263     case VM_SV32:
1264       levels = 2;
1265       ptidxbits = 10;
1266       ptesize = 4;
1267       break;
1268     case VM_SV39:
1269       levels = 3;
1270       ptidxbits = 9;
1271       ptesize = 8;
1272       break;
1273     case VM_SV48:
1274       levels = 4;
1275       ptidxbits = 9;
1276       ptesize = 8;
1277       break;
1278
1279     default:
1280       {
1281         char buf[100];
1282         sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
1283         die(buf);
1284         return true;        // die doesn't return, but gcc doesn't know that.
1285       }
1286   }
1287
1288   // Handle page tables here. There's a bunch of duplicated code with
1289   // collect_translation_info_op_t. :-(
1290   reg_t base = sptbr << PGSHIFT;
1291   int ptshift = (levels - 1) * ptidxbits;
1292   for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1293     reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1294
1295     reg_t pte_addr = base + idx * ptesize;
1296     auto it = pte_cache.find(pte_addr);
1297     if (it == pte_cache.end()) {
1298       fprintf(stderr, "ERROR: gdbserver tried to translate 0x%lx without first "
1299           "collecting the relevant PTEs.\n", vaddr);
1300       die("gdbserver_t::translate()");
1301     }
1302
1303     reg_t pte = pte_cache[pte_addr];
1304     reg_t ppn = pte >> PTE_PPN_SHIFT;
1305
1306     if (PTE_TABLE(pte)) { // next level of page table
1307       base = ppn << PGSHIFT;
1308     } else {
1309       // We've collected all the data required for the translation.
1310       reg_t vpn = vaddr >> PGSHIFT;
1311       reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
1312       paddr += vaddr & (PGSIZE-1);
1313       D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
1314       return paddr;
1315     }
1316   }
1317
1318   fprintf(stderr, "ERROR: gdbserver tried to translate 0x%lx but the relevant "
1319       "PTEs are invalid.\n", vaddr);
1320   // TODO: Is it better to throw an exception here?
1321   return -1;
1322 }
1323
1324 unsigned int gdbserver_t::privilege_mode()
1325 {
1326   unsigned int mode = get_field(dcsr, DCSR_PRV);
1327   if (get_field(mstatus, MSTATUS_MPRV))
1328     mode = get_field(mstatus, MSTATUS_MPP);
1329   return mode;
1330 }
1331
1332 unsigned int gdbserver_t::virtual_memory()
1333 {
1334   unsigned int mode = privilege_mode();
1335   if (mode == PRV_M)
1336     return VM_MBARE;
1337   return get_field(mstatus, MSTATUS_VM);
1338 }
1339
1340 void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
1341 {
1342   sim->debug_module.ram_write32(index, value);
1343 }
1344
1345 void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
1346 {
1347   dr_write32(index, value);
1348   dr_write32(index+1, value >> 32);
1349 }
1350
1351 void gdbserver_t::dr_write(enum slot slot, uint64_t value)
1352 {
1353   switch (xlen) {
1354     case 32:
1355       dr_write32(slot_offset32[slot], value);
1356       break;
1357     case 64:
1358       dr_write64(slot_offset64[slot], value);
1359       break;
1360     case 128:
1361     default:
1362       abort();
1363   }
1364 }
1365
1366 void gdbserver_t::dr_write_jump(unsigned int index)
1367 {
1368   dr_write32(index, jal(0,
1369         (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
1370 }
1371
1372 void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
1373 {
1374   assert(slot != SLOT_INST0 || index > 2);
1375   assert(slot != SLOT_DATA0 || index < 4 || index > 6);
1376   assert(slot != SLOT_DATA1 || index < 5 || index > 10);
1377   assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
1378   switch (xlen) {
1379     case 32:
1380       return dr_write32(index,
1381           sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1382     case 64:
1383       return dr_write32(index,
1384           sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1385     case 128:
1386       return dr_write32(index,
1387           sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1388     default:
1389       fprintf(stderr, "xlen is %d!\n", xlen);
1390       abort();
1391   }
1392 }
1393
1394 void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
1395 {
1396   switch (xlen) {
1397     case 32:
1398       return dr_write32(index,
1399           lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1400     case 64:
1401       return dr_write32(index,
1402           ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1403     case 128:
1404       return dr_write32(index,
1405           lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1406     default:
1407       fprintf(stderr, "xlen is %d!\n", xlen);
1408       abort();
1409   }
1410 }
1411
1412 uint32_t gdbserver_t::dr_read32(unsigned int index)
1413 {
1414   uint32_t value = sim->debug_module.ram_read32(index);
1415   D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
1416   return value;
1417 }
1418
1419 uint64_t gdbserver_t::dr_read64(unsigned int index)
1420 {
1421   return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
1422 }
1423
1424 uint64_t gdbserver_t::dr_read(enum slot slot)
1425 {
1426   switch (xlen) {
1427     case 32:
1428       return dr_read32(slot_offset32[slot]);
1429     case 64:
1430       return dr_read64(slot_offset64[slot]);
1431     case 128:
1432       abort();
1433     default:
1434       abort();
1435   }
1436 }
1437
1438 void gdbserver_t::add_operation(operation_t* operation)
1439 {
1440   operation_queue.push(operation);
1441 }
1442
1443 void gdbserver_t::accept()
1444 {
1445   client_fd = ::accept(socket_fd, NULL, NULL);
1446   if (client_fd == -1) {
1447     if (errno == EAGAIN) {
1448       // No client waiting to connect right now.
1449     } else {
1450       fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
1451           errno);
1452       abort();
1453     }
1454   } else {
1455     fcntl(client_fd, F_SETFL, O_NONBLOCK);
1456
1457     expect_ack = false;
1458     extended_mode = false;
1459
1460     // gdb wants the core to be halted when it attaches.
1461     add_operation(new halt_op_t(*this));
1462   }
1463 }
1464
1465 void gdbserver_t::read()
1466 {
1467   // Reading from a non-blocking socket still blocks if there is no data
1468   // available.
1469
1470   size_t count = recv_buf.contiguous_empty_size();
1471   assert(count > 0);
1472   ssize_t bytes = ::read(client_fd, recv_buf.contiguous_empty(), count);
1473   if (bytes == -1) {
1474     if (errno == EAGAIN) {
1475       // We'll try again the next call.
1476     } else {
1477       fprintf(stderr, "failed to read on socket: %s (%d)\n", strerror(errno), errno);
1478       abort();
1479     }
1480   } else if (bytes == 0) {
1481     // The remote disconnected.
1482     client_fd = 0;
1483     processor_t *p = sim->get_core(0);
1484     // TODO p->set_halted(false, HR_NONE);
1485     recv_buf.reset();
1486     send_buf.reset();
1487   } else {
1488     recv_buf.data_added(bytes);
1489   }
1490 }
1491
1492 void gdbserver_t::write()
1493 {
1494   if (send_buf.empty())
1495     return;
1496
1497   while (!send_buf.empty()) {
1498     unsigned int count = send_buf.contiguous_data_size();
1499     assert(count > 0);
1500     ssize_t bytes = ::write(client_fd, send_buf.contiguous_data(), count);
1501     if (bytes == -1) {
1502       fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
1503       abort();
1504     } else if (bytes == 0) {
1505       // Client can't take any more data right now.
1506       break;
1507     } else {
1508       D(fprintf(stderr, "wrote %ld bytes: ", bytes));
1509       for (unsigned int i = 0; i < bytes; i++) {
1510         D(fprintf(stderr, "%c", send_buf[i]));
1511       }
1512       D(fprintf(stderr, "\n"));
1513       send_buf.consume(bytes);
1514     }
1515   }
1516 }
1517
1518 void print_packet(const std::vector<uint8_t> &packet)
1519 {
1520   for (uint8_t c : packet) {
1521     if (c >= ' ' and c <= '~')
1522       fprintf(stderr, "%c", c);
1523     else
1524       fprintf(stderr, "\\x%02x", c);
1525   }
1526   fprintf(stderr, "\n");
1527 }
1528
1529 uint8_t compute_checksum(const std::vector<uint8_t> &packet)
1530 {
1531   uint8_t checksum = 0;
1532   for (auto i = packet.begin() + 1; i != packet.end() - 3; i++ ) {
1533     checksum += *i;
1534   }
1535   return checksum;
1536 }
1537
1538 uint8_t character_hex_value(uint8_t character)
1539 {
1540   if (character >= '0' && character <= '9')
1541     return character - '0';
1542   if (character >= 'a' && character <= 'f')
1543     return 10 + character - 'a';
1544   if (character >= 'A' && character <= 'F')
1545     return 10 + character - 'A';
1546   return 0xff;
1547 }
1548
1549 uint8_t extract_checksum(const std::vector<uint8_t> &packet)
1550 {
1551   return character_hex_value(*(packet.end() - 1)) +
1552     16 * character_hex_value(*(packet.end() - 2));
1553 }
1554
1555 void gdbserver_t::process_requests()
1556 {
1557   // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1558
1559   while (!recv_buf.empty()) {
1560     std::vector<uint8_t> packet;
1561     for (unsigned int i = 0; i < recv_buf.size(); i++) {
1562       uint8_t b = recv_buf[i];
1563
1564       if (packet.empty() && expect_ack && b == '+') {
1565         recv_buf.consume(1);
1566         break;
1567       }
1568
1569       if (packet.empty() && b == 3) {
1570         D(fprintf(stderr, "Received interrupt\n"));
1571         recv_buf.consume(1);
1572         handle_interrupt();
1573         break;
1574       }
1575
1576       if (b == '$') {
1577         // Start of new packet.
1578         if (!packet.empty()) {
1579           fprintf(stderr, "Received malformed %ld-byte packet from debug client: ",
1580               packet.size());
1581           print_packet(packet);
1582           recv_buf.consume(i);
1583           break;
1584         }
1585       }
1586
1587       packet.push_back(b);
1588
1589       // Packets consist of $<packet-data>#<checksum>
1590       // where <checksum> is
1591       if (packet.size() >= 4 &&
1592           packet[packet.size()-3] == '#') {
1593         handle_packet(packet);
1594         recv_buf.consume(i+1);
1595         break;
1596       }
1597     }
1598     // There's a partial packet in the buffer. Wait until we get more data to
1599     // process it.
1600     if (packet.size()) {
1601       break;
1602     }
1603   }
1604 }
1605
1606 void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
1607 {
1608   send_packet("S00");
1609 }
1610
1611 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
1612 {
1613   add_operation(new general_registers_read_op_t(*this));
1614 }
1615
1616 void gdbserver_t::set_interrupt(uint32_t hartid) {
1617   sim->debug_module.set_interrupt(hartid);
1618 }
1619
1620 // First byte is the most-significant one.
1621 // Eg. "08675309" becomes 0x08675309.
1622 uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
1623     std::vector<uint8_t>::const_iterator end)
1624 {
1625   uint64_t value = 0;
1626
1627   while (iter != end) {
1628     uint8_t c = *iter;
1629     uint64_t c_value = character_hex_value(c);
1630     if (c_value > 15)
1631       break;
1632     iter++;
1633     value <<= 4;
1634     value += c_value;
1635   }
1636   return value;
1637 }
1638
1639 // First byte is the least-significant one.
1640 // Eg. "08675309" becomes 0x09536708
1641 uint64_t consume_hex_number_le(std::vector<uint8_t>::const_iterator &iter,
1642     std::vector<uint8_t>::const_iterator end)
1643 {
1644   uint64_t value = 0;
1645   unsigned int shift = 4;
1646
1647   while (iter != end) {
1648     uint8_t c = *iter;
1649     uint64_t c_value = character_hex_value(c);
1650     if (c_value > 15)
1651       break;
1652     iter++;
1653     value |= c_value << shift;
1654     if ((shift % 8) == 0)
1655       shift += 12;
1656     else
1657       shift -= 4;
1658   }
1659   return value;
1660 }
1661
1662 void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
1663     std::vector<uint8_t>::const_iterator end, uint8_t separator)
1664 {
1665   while (iter != end && *iter != separator) {
1666     str.append(1, (char) *iter);
1667     iter++;
1668   }
1669 }
1670
1671 void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
1672 {
1673   // p n
1674
1675   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1676   unsigned int n = consume_hex_number(iter, packet.end());
1677   if (*iter != '#')
1678     return send_packet("E01");
1679
1680   add_operation(new register_read_op_t(*this, n));
1681 }
1682
1683 void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
1684 {
1685   // P n...=r...
1686
1687   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1688   unsigned int n = consume_hex_number(iter, packet.end());
1689   if (*iter != '=')
1690     return send_packet("E05");
1691   iter++;
1692
1693   reg_t value = consume_hex_number_le(iter, packet.end());
1694   if (*iter != '#')
1695     return send_packet("E06");
1696
1697   processor_t *p = sim->get_core(0);
1698
1699   add_operation(new register_write_op_t(*this, n, value));
1700
1701   return send_packet("OK");
1702 }
1703
1704 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
1705 {
1706   // m addr,length
1707   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1708   reg_t address = consume_hex_number(iter, packet.end());
1709   if (*iter != ',')
1710     return send_packet("E10");
1711   iter++;
1712   reg_t length = consume_hex_number(iter, packet.end());
1713   if (*iter != '#')
1714     return send_packet("E11");
1715
1716   add_operation(new collect_translation_info_op_t(*this, address, length));
1717   add_operation(new memory_read_op_t(*this, address, length));
1718 }
1719
1720 void gdbserver_t::handle_memory_binary_write(const std::vector<uint8_t> &packet)
1721 {
1722   // X addr,length:XX...
1723   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1724   reg_t address = consume_hex_number(iter, packet.end());
1725   if (*iter != ',')
1726     return send_packet("E20");
1727   iter++;
1728   reg_t length = consume_hex_number(iter, packet.end());
1729   if (*iter != ':')
1730     return send_packet("E21");
1731   iter++;
1732
1733   if (length == 0) {
1734     return send_packet("OK");
1735   }
1736
1737   unsigned char *data = new unsigned char[length];
1738   for (unsigned int i = 0; i < length; i++) {
1739     if (iter == packet.end()) {
1740       return send_packet("E22");
1741     }
1742     uint8_t c = *iter;
1743     iter++;
1744     if (c == '}') {
1745       // The binary data representation uses 7d (ascii ‘}’) as an escape
1746       // character. Any escaped byte is transmitted as the escape character
1747       // followed by the original character XORed with 0x20. For example, the
1748       // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1749       // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1750       // be escaped.
1751       if (iter == packet.end()) {
1752         return send_packet("E23");
1753       }
1754       c = (*iter) ^ 0x20;
1755       iter++;
1756     }
1757     data[i] = c;
1758   }
1759   if (*iter != '#')
1760     return send_packet("E4b"); // EOVERFLOW
1761
1762   add_operation(new collect_translation_info_op_t(*this, address, length));
1763   add_operation(new memory_write_op_t(*this, address, length, data));
1764 }
1765
1766 void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
1767 {
1768   // c [addr]
1769   processor_t *p = sim->get_core(0);
1770   if (packet[2] != '#') {
1771     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1772     dpc = consume_hex_number(iter, packet.end());
1773     if (*iter != '#')
1774       return send_packet("E30");
1775   }
1776
1777   add_operation(new maybe_restore_tselect_op_t(*this));
1778   add_operation(new continue_op_t(*this, false));
1779 }
1780
1781 void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
1782 {
1783   // s [addr]
1784   if (packet[2] != '#') {
1785     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1786     die("handle_step");
1787     //p->state.pc = consume_hex_number(iter, packet.end());
1788     if (*iter != '#')
1789       return send_packet("E40");
1790   }
1791
1792   add_operation(new maybe_restore_tselect_op_t(*this));
1793   add_operation(new continue_op_t(*this, true));
1794 }
1795
1796 void gdbserver_t::handle_kill(const std::vector<uint8_t> &packet)
1797 {
1798   // k
1799   // The exact effect of this packet is not specified.
1800   // Looks like OpenOCD disconnects?
1801   // TODO
1802 }
1803
1804 void gdbserver_t::handle_extended(const std::vector<uint8_t> &packet)
1805 {
1806   // Enable extended mode. In extended mode, the remote server is made
1807   // persistent. The ‘R’ packet is used to restart the program being debugged.
1808   send_packet("OK");
1809   extended_mode = true;
1810 }
1811
1812 void gdbserver_t::software_breakpoint_insert(reg_t vaddr, unsigned int size)
1813 {
1814   fence_i_required = true;
1815   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1816   unsigned char* inst = new unsigned char[4];
1817   if (size == 2) {
1818     inst[0] = C_EBREAK & 0xff;
1819     inst[1] = (C_EBREAK >> 8) & 0xff;
1820   } else {
1821     inst[0] = EBREAK & 0xff;
1822     inst[1] = (EBREAK >> 8) & 0xff;
1823     inst[2] = (EBREAK >> 16) & 0xff;
1824     inst[3] = (EBREAK >> 24) & 0xff;
1825   }
1826
1827   software_breakpoint_t bp = {
1828     .vaddr = vaddr,
1829     .size = size
1830   };
1831   software_breakpoints[vaddr] = bp;
1832   add_operation(new memory_read_op_t(*this, bp.vaddr, bp.size,
1833         software_breakpoints[bp.vaddr].instruction));
1834   add_operation(new memory_write_op_t(*this, bp.vaddr, bp.size, inst));
1835 }
1836
1837 void gdbserver_t::software_breakpoint_remove(reg_t vaddr, unsigned int size)
1838 {
1839   fence_i_required = true;
1840   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1841
1842   software_breakpoint_t found_bp = software_breakpoints[vaddr];
1843   unsigned char* instruction = new unsigned char[4];
1844   memcpy(instruction, found_bp.instruction, 4);
1845   add_operation(new memory_write_op_t(*this, found_bp.vaddr,
1846         found_bp.size, instruction));
1847   software_breakpoints.erase(vaddr);
1848 }
1849
1850 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t &bp)
1851 {
1852   add_operation(new maybe_save_tselect_op_t(*this));
1853   add_operation(new hardware_breakpoint_insert_op_t(*this, bp));
1854 }
1855
1856 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t &bp)
1857 {
1858   add_operation(new maybe_save_tselect_op_t(*this));
1859   hardware_breakpoint_t found = *hardware_breakpoints.find(bp);
1860   add_operation(new hardware_breakpoint_remove_op_t(*this, found));
1861 }
1862
1863 void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
1864 {
1865   // insert: Z type,addr,length
1866   // remove: z type,addr,length
1867
1868   // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1869   // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1870   // length is in bytes. For a software breakpoint, length specifies the size
1871   // of the instruction to be patched. For hardware breakpoints and watchpoints
1872   // length specifies the memory region to be monitored. To avoid potential
1873   // problems with duplicate packets, the operations should be implemented in
1874   // an idempotent way.
1875
1876   bool insert = (packet[1] == 'Z');
1877   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1878   gdb_breakpoint_type_t type = static_cast<gdb_breakpoint_type_t>(
1879       consume_hex_number(iter, packet.end()));
1880   if (*iter != ',')
1881     return send_packet("E50");
1882   iter++;
1883   reg_t address = consume_hex_number(iter, packet.end());
1884   if (*iter != ',')
1885     return send_packet("E51");
1886   iter++;
1887   unsigned int size = consume_hex_number(iter, packet.end());
1888   // There may be more options after a ; here, but we don't support that.
1889   if (*iter != '#')
1890     return send_packet("E52");
1891
1892   switch (type) {
1893     case GB_SOFTWARE:
1894       if (size != 2 && size != 4) {
1895         return send_packet("E53");
1896       }
1897       if (insert) {
1898         software_breakpoint_insert(address, size);
1899       } else {
1900         software_breakpoint_remove(address, size);
1901       }
1902       break;
1903
1904     case GB_HARDWARE:
1905     case GB_WRITE:
1906     case GB_READ:
1907     case GB_ACCESS:
1908       {
1909         hardware_breakpoint_t bp = {
1910           .vaddr = address,
1911           .size = size
1912         };
1913         bp.load = (type == GB_READ || type == GB_ACCESS);
1914         bp.store = (type == GB_WRITE || type == GB_ACCESS);
1915         bp.execute = (type == GB_HARDWARE || type == GB_ACCESS);
1916         if (insert) {
1917           hardware_breakpoint_insert(bp);
1918           // Insert might fail if there's no space, so the insert operation will
1919           // send its own OK (or not).
1920           return;
1921         } else {
1922           hardware_breakpoint_remove(bp);
1923         }
1924       }
1925       break;
1926
1927     default:
1928       return send_packet("E56");
1929   }
1930
1931   return send_packet("OK");
1932 }
1933
1934 void gdbserver_t::handle_query(const std::vector<uint8_t> &packet)
1935 {
1936   std::string name;
1937   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1938
1939   consume_string(name, iter, packet.end(), ':');
1940   if (iter != packet.end())
1941     iter++;
1942   if (name == "Supported") {
1943     start_packet();
1944     while (iter != packet.end()) {
1945       std::string feature;
1946       consume_string(feature, iter, packet.end(), ';');
1947       if (iter != packet.end())
1948         iter++;
1949       if (feature == "swbreak+") {
1950         send("swbreak+;");
1951       }
1952     }
1953     send("PacketSize=131072;");
1954     return end_packet();
1955   }
1956
1957   D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
1958   return send_packet("");
1959 }
1960
1961 void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet)
1962 {
1963   if (compute_checksum(packet) != extract_checksum(packet)) {
1964     fprintf(stderr, "Received %ld-byte packet with invalid checksum\n", packet.size());
1965     fprintf(stderr, "Computed checksum: %x\n", compute_checksum(packet));
1966     print_packet(packet);
1967     send("-");
1968     return;
1969   }
1970
1971   D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
1972   D(print_packet(packet));
1973   send("+");
1974
1975   switch (packet[1]) {
1976     case '!':
1977       return handle_extended(packet);
1978     case '?':
1979       return handle_halt_reason(packet);
1980     case 'g':
1981       return handle_general_registers_read(packet);
1982 //    case 'k':
1983 //      return handle_kill(packet);
1984     case 'm':
1985       return handle_memory_read(packet);
1986 //    case 'M':
1987 //      return handle_memory_write(packet);
1988     case 'X':
1989       return handle_memory_binary_write(packet);
1990     case 'p':
1991       return handle_register_read(packet);
1992     case 'P':
1993       return handle_register_write(packet);
1994     case 'c':
1995       return handle_continue(packet);
1996     case 's':
1997       return handle_step(packet);
1998     case 'z':
1999     case 'Z':
2000       return handle_breakpoint(packet);
2001     case 'q':
2002     case 'Q':
2003       return handle_query(packet);
2004   }
2005
2006   // Not supported.
2007   D(fprintf(stderr, "** Unsupported packet: "));
2008   D(print_packet(packet));
2009   send_packet("");
2010 }
2011
2012 void gdbserver_t::handle_interrupt()
2013 {
2014   processor_t *p = sim->get_core(0);
2015   add_operation(new halt_op_t(*this, true));
2016 }
2017
2018 void gdbserver_t::handle()
2019 {
2020   if (client_fd > 0) {
2021     processor_t *p = sim->get_core(0);
2022
2023     bool interrupt = sim->debug_module.get_interrupt(0);
2024
2025     if (!interrupt && !operation_queue.empty()) {
2026       operation_t *operation = operation_queue.front();
2027       if (operation->step()) {
2028         operation_queue.pop();
2029         delete operation;
2030       }
2031     }
2032
2033     bool halt_notification = sim->debug_module.get_halt_notification(0);
2034     if (halt_notification) {
2035       sim->debug_module.clear_halt_notification(0);
2036       add_operation(new halt_op_t(*this, true));
2037     }
2038
2039     this->read();
2040     this->write();
2041
2042   } else {
2043     this->accept();
2044   }
2045
2046   if (operation_queue.empty()) {
2047     this->process_requests();
2048   }
2049 }
2050
2051 void gdbserver_t::send(const char* msg)
2052 {
2053   unsigned int length = strlen(msg);
2054   for (const char *c = msg; *c; c++)
2055     running_checksum += *c;
2056   send_buf.append((const uint8_t *) msg, length);
2057 }
2058
2059 void gdbserver_t::send(uint64_t value)
2060 {
2061   char buffer[3];
2062   for (unsigned int i = 0; i < 8; i++) {
2063     sprintf(buffer, "%02x", (int) (value & 0xff));
2064     send(buffer);
2065     value >>= 8;
2066   }
2067 }
2068
2069 void gdbserver_t::send(uint32_t value)
2070 {
2071   char buffer[3];
2072   for (unsigned int i = 0; i < 4; i++) {
2073     sprintf(buffer, "%02x", (int) (value & 0xff));
2074     send(buffer);
2075     value >>= 8;
2076   }
2077 }
2078
2079 void gdbserver_t::send(uint8_t value)
2080 {
2081   char buffer[3];
2082   sprintf(buffer, "%02x", (int) value);
2083   send(buffer);
2084 }
2085
2086 void gdbserver_t::send_packet(const char* data)
2087 {
2088   start_packet();
2089   send(data);
2090   end_packet();
2091   expect_ack = true;
2092 }
2093
2094 void gdbserver_t::start_packet()
2095 {
2096   send("$");
2097   running_checksum = 0;
2098 }
2099
2100 void gdbserver_t::end_packet(const char* data)
2101 {
2102   if (data) {
2103     send(data);
2104   }
2105
2106   char checksum_string[4];
2107   sprintf(checksum_string, "#%02x", running_checksum);
2108   send(checksum_string);
2109   expect_ack = true;
2110 }