6 #include <sys/socket.h>
17 #include "gdbserver.h"
20 #define C_EBREAK 0x9002
21 #define EBREAK 0x00100073
23 //////////////////////////////////////// Utility Functions
32 void die(const char* msg
)
34 fprintf(stderr
, "gdbserver code died: %s\n", msg
);
38 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
39 // its source tree. We must interpret the numbers the same here.
51 //////////////////////////////////////// Functions to generate RISC-V opcodes.
53 // TODO: Does this already exist somewhere?
56 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
57 // spec says it should be 2 and 3.
60 static uint32_t bits(uint32_t value
, unsigned int hi
, unsigned int lo
) {
61 return (value
>> lo
) & ((1 << (hi
+1-lo
)) - 1);
64 static uint32_t bit(uint32_t value
, unsigned int b
) {
65 return (value
>> b
) & 1;
68 static uint32_t jal(unsigned int rd
, uint32_t imm
) {
69 return (bit(imm
, 20) << 31) |
70 (bits(imm
, 10, 1) << 21) |
71 (bit(imm
, 11) << 20) |
72 (bits(imm
, 19, 12) << 12) |
77 static uint32_t csrsi(unsigned int csr
, uint16_t imm
) {
79 (bits(imm
, 4, 0) << 15) |
83 static uint32_t csrci(unsigned int csr
, uint16_t imm
) {
85 (bits(imm
, 4, 0) << 15) |
89 static uint32_t csrr(unsigned int rd
, unsigned int csr
) {
90 return (csr
<< 20) | (rd
<< 7) | MATCH_CSRRS
;
93 static uint32_t csrw(unsigned int source
, unsigned int csr
) {
94 return (csr
<< 20) | (source
<< 15) | MATCH_CSRRW
;
97 static uint32_t fence_i()
102 static uint32_t sb(unsigned int src
, unsigned int base
, uint16_t offset
)
104 return (bits(offset
, 11, 5) << 25) |
107 (bits(offset
, 4, 0) << 7) |
111 static uint32_t sh(unsigned int src
, unsigned int base
, uint16_t offset
)
113 return (bits(offset
, 11, 5) << 25) |
116 (bits(offset
, 4, 0) << 7) |
120 static uint32_t sw(unsigned int src
, unsigned int base
, uint16_t offset
)
122 return (bits(offset
, 11, 5) << 25) |
125 (bits(offset
, 4, 0) << 7) |
129 static uint32_t sd(unsigned int src
, unsigned int base
, uint16_t offset
)
131 return (bits(offset
, 11, 5) << 25) |
132 (bits(src
, 4, 0) << 20) |
134 (bits(offset
, 4, 0) << 7) |
138 static uint32_t sq(unsigned int src
, unsigned int base
, uint16_t offset
)
141 return (bits(offset
, 11, 5) << 25) |
142 (bits(src
, 4, 0) << 20) |
144 (bits(offset
, 4, 0) << 7) |
151 static uint32_t lq(unsigned int rd
, unsigned int base
, uint16_t offset
)
154 return (bits(offset
, 11, 0) << 20) |
156 (bits(rd
, 4, 0) << 7) |
163 static uint32_t ld(unsigned int rd
, unsigned int base
, uint16_t offset
)
165 return (bits(offset
, 11, 0) << 20) |
167 (bits(rd
, 4, 0) << 7) |
171 static uint32_t lw(unsigned int rd
, unsigned int base
, uint16_t offset
)
173 return (bits(offset
, 11, 0) << 20) |
175 (bits(rd
, 4, 0) << 7) |
179 static uint32_t lh(unsigned int rd
, unsigned int base
, uint16_t offset
)
181 return (bits(offset
, 11, 0) << 20) |
183 (bits(rd
, 4, 0) << 7) |
187 static uint32_t lb(unsigned int rd
, unsigned int base
, uint16_t offset
)
189 return (bits(offset
, 11, 0) << 20) |
191 (bits(rd
, 4, 0) << 7) |
195 static uint32_t fsw(unsigned int src
, unsigned int base
, uint16_t offset
)
197 return (bits(offset
, 11, 5) << 25) |
198 (bits(src
, 4, 0) << 20) |
200 (bits(offset
, 4, 0) << 7) |
204 static uint32_t fsd(unsigned int src
, unsigned int base
, uint16_t offset
)
206 return (bits(offset
, 11, 5) << 25) |
207 (bits(src
, 4, 0) << 20) |
209 (bits(offset
, 4, 0) << 7) |
213 static uint32_t flw(unsigned int src
, unsigned int base
, uint16_t offset
)
215 return (bits(offset
, 11, 5) << 25) |
216 (bits(src
, 4, 0) << 20) |
218 (bits(offset
, 4, 0) << 7) |
222 static uint32_t fld(unsigned int src
, unsigned int base
, uint16_t offset
)
224 return (bits(offset
, 11, 5) << 25) |
225 (bits(src
, 4, 0) << 20) |
227 (bits(offset
, 4, 0) << 7) |
231 static uint32_t addi(unsigned int dest
, unsigned int src
, uint16_t imm
)
233 return (bits(imm
, 11, 0) << 20) |
239 static uint32_t ori(unsigned int dest
, unsigned int src
, uint16_t imm
)
241 return (bits(imm
, 11, 0) << 20) |
247 static uint32_t xori(unsigned int dest
, unsigned int src
, uint16_t imm
)
249 return (bits(imm
, 11, 0) << 20) |
255 static uint32_t srli(unsigned int dest
, unsigned int src
, uint8_t shamt
)
257 return (bits(shamt
, 4, 0) << 20) |
264 static uint32_t nop()
266 return addi(0, 0, 0);
269 template <typename T
>
270 unsigned int circular_buffer_t
<T
>::size() const
275 return end
+ capacity
- start
;
278 template <typename T
>
279 void circular_buffer_t
<T
>::consume(unsigned int bytes
)
281 start
= (start
+ bytes
) % capacity
;
284 template <typename T
>
285 unsigned int circular_buffer_t
<T
>::contiguous_empty_size() const
289 return capacity
- end
- 1;
291 return capacity
- end
;
293 return start
- end
- 1;
296 template <typename T
>
297 unsigned int circular_buffer_t
<T
>::contiguous_data_size() const
302 return capacity
- start
;
305 template <typename T
>
306 void circular_buffer_t
<T
>::data_added(unsigned int bytes
)
309 assert(end
<= capacity
);
314 template <typename T
>
315 void circular_buffer_t
<T
>::reset()
321 template <typename T
>
322 void circular_buffer_t
<T
>::append(const T
*src
, unsigned int count
)
324 unsigned int copy
= std::min(count
, contiguous_empty_size());
325 memcpy(contiguous_empty(), src
, copy
* sizeof(T
));
329 assert(count
< contiguous_empty_size());
330 memcpy(contiguous_empty(), src
, count
* sizeof(T
));
335 ////////////////////////////// Debug Operations
337 class halt_op_t
: public operation_t
340 halt_op_t(gdbserver_t
& gdbserver
, bool send_status
=false) :
341 operation_t(gdbserver
), send_status(send_status
),
344 void write_dpc_program() {
345 gs
.dr_write32(0, csrsi(CSR_DCSR
, DCSR_HALT
));
346 gs
.dr_write32(1, csrr(S0
, CSR_DPC
));
347 gs
.dr_write_store(2, S0
, SLOT_DATA0
);
352 bool perform_step(unsigned int step
) {
354 gs
.tselect_valid
= false;
357 gs
.dr_write32(0, xori(S1
, ZERO
, -1));
358 gs
.dr_write32(1, srli(S1
, S1
, 31));
359 // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
360 gs
.dr_write32(2, sw(S1
, ZERO
, DEBUG_RAM_START
));
361 gs
.dr_write32(3, srli(S1
, S1
, 31));
362 // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
363 gs
.dr_write32(4, sw(S1
, ZERO
, DEBUG_RAM_START
+ 4));
376 uint32_t word0
= gs
.dr_read32(0);
377 uint32_t word1
= gs
.dr_read32(1);
379 if (word0
== 1 && word1
== 0) {
381 } else if (word0
== 0xffffffff && word1
== 3) {
383 } else if (word0
== 0xffffffff && word1
== 0xffffffff) {
393 gs
.dpc
= gs
.dr_read(SLOT_DATA0
);
394 gs
.dr_write32(0, csrr(S0
, CSR_MSTATUS
));
395 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
402 gs
.mstatus
= gs
.dr_read(SLOT_DATA0
);
403 gs
.dr_write32(0, csrr(S0
, CSR_DCSR
));
404 gs
.dr_write32(1, sw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
411 gs
.dcsr
= gs
.dr_read32(4);
413 gs
.sptbr_valid
= false;
414 gs
.pte_cache
.clear();
417 switch (get_field(gs
.dcsr
, DCSR_CAUSE
)) {
418 case DCSR_CAUSE_NONE
:
419 fprintf(stderr
, "Internal error. Processor halted without reason.\n");
422 case DCSR_CAUSE_DEBUGINT
:
423 gs
.send_packet("S02"); // Pretend program received SIGINT.
426 case DCSR_CAUSE_HWBP
:
427 case DCSR_CAUSE_STEP
:
428 case DCSR_CAUSE_HALT
:
429 // There's no gdb code for this.
430 gs
.send_packet("T05");
432 case DCSR_CAUSE_SWBP
:
433 gs
.send_packet("T05swbreak:;");
455 class continue_op_t
: public operation_t
458 continue_op_t(gdbserver_t
& gdbserver
, bool single_step
) :
459 operation_t(gdbserver
), single_step(single_step
) {};
461 bool perform_step(unsigned int step
) {
462 D(fprintf(stderr
, "continue step %d\n", step
));
465 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
466 gs
.dr_write32(1, csrw(S0
, CSR_DPC
));
467 // TODO: Isn't there a fence.i in Debug ROM already?
468 if (gs
.fence_i_required
) {
469 gs
.dr_write32(2, fence_i());
471 gs
.fence_i_required
= false;
475 gs
.dr_write(SLOT_DATA0
, gs
.dpc
);
480 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
481 gs
.dr_write32(1, csrw(S0
, CSR_MSTATUS
));
483 gs
.dr_write(SLOT_DATA0
, gs
.mstatus
);
488 gs
.dr_write32(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+16));
489 gs
.dr_write32(1, csrw(S0
, CSR_DCSR
));
492 reg_t dcsr
= set_field(gs
.dcsr
, DCSR_HALT
, 0);
493 dcsr
= set_field(dcsr
, DCSR_STEP
, single_step
);
494 // Software breakpoints should go here.
495 dcsr
= set_field(dcsr
, DCSR_EBREAKM
, 1);
496 dcsr
= set_field(dcsr
, DCSR_EBREAKH
, 1);
497 dcsr
= set_field(dcsr
, DCSR_EBREAKS
, 1);
498 dcsr
= set_field(dcsr
, DCSR_EBREAKU
, 1);
499 gs
.dr_write32(4, dcsr
);
511 class general_registers_read_op_t
: public operation_t
513 // Register order that gdb expects is:
514 // "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
515 // "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
516 // "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
517 // "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
519 // Each byte of register data is described by two hex digits. The bytes with
520 // the register are transmitted in target byte order. The size of each
521 // register and their position within the ‘g’ packet are determined by the
522 // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
523 // gdbarch_register_name.
526 general_registers_read_op_t(gdbserver_t
& gdbserver
) :
527 operation_t(gdbserver
) {};
529 bool perform_step(unsigned int step
)
531 D(fprintf(stderr
, "register_read step %d\n", step
));
535 // x0 is always zero.
537 gs
.send((uint32_t) 0);
539 gs
.send((uint64_t) 0);
542 gs
.dr_write_store(0, 1, SLOT_DATA0
);
543 gs
.dr_write_store(1, 2, SLOT_DATA1
);
550 gs
.send((uint32_t) gs
.dr_read(SLOT_DATA0
));
552 gs
.send((uint64_t) gs
.dr_read(SLOT_DATA0
));
560 gs
.send((uint32_t) gs
.dr_read(SLOT_DATA1
));
562 gs
.send((uint64_t) gs
.dr_read(SLOT_DATA1
));
565 unsigned int current_reg
= 2 * step
+ 1;
567 if (current_reg
== S1
) {
568 gs
.dr_write_load(i
++, S1
, SLOT_DATA_LAST
);
570 gs
.dr_write_store(i
++, current_reg
, SLOT_DATA0
);
571 if (current_reg
+ 1 == S0
) {
572 gs
.dr_write32(i
++, csrr(S0
, CSR_DSCRATCH
));
575 gs
.dr_write_store(i
++, current_reg
+1, SLOT_DATA1
);
584 class register_read_op_t
: public operation_t
587 register_read_op_t(gdbserver_t
& gdbserver
, unsigned int reg
) :
588 operation_t(gdbserver
), reg(reg
) {};
590 bool perform_step(unsigned int step
)
594 if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
595 die("handle_register_read");
596 // send(p->state.XPR[reg - REG_XPR0]);
597 } else if (reg
== REG_PC
) {
600 gs
.send((uint32_t) gs
.dpc
);
606 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
607 // send(p->state.FPR[reg - REG_FPR0]);
609 gs
.dr_write32(0, fsw(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
611 gs
.dr_write32(0, fsd(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
614 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
615 gs
.dr_write32(0, csrr(S0
, reg
- REG_CSR0
));
616 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
618 // If we hit an exception reading the CSR, we'll end up returning ~0 as
619 // the register's value, which is what we want. (Right?)
620 gs
.dr_write(SLOT_DATA0
, ~(uint64_t) 0);
621 } else if (reg
== REG_PRIV
) {
623 gs
.send((uint8_t) get_field(gs
.dcsr
, DCSR_PRV
));
627 gs
.send_packet("E02");
636 gs
.send(gs
.dr_read32(4));
638 gs
.send(gs
.dr_read(SLOT_DATA0
));
650 class register_write_op_t
: public operation_t
653 register_write_op_t(gdbserver_t
& gdbserver
, unsigned int reg
, reg_t value
) :
654 operation_t(gdbserver
), reg(reg
), value(value
) {};
656 bool perform_step(unsigned int step
)
658 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
659 gs
.dr_write(SLOT_DATA0
, value
);
661 gs
.dr_write32(1, csrw(S0
, CSR_DSCRATCH
));
663 } else if (reg
== S1
) {
664 gs
.dr_write_store(1, S0
, SLOT_DATA_LAST
);
666 } else if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
667 gs
.dr_write32(1, addi(reg
, S0
, 0));
669 } else if (reg
== REG_PC
) {
672 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
674 gs
.dr_write32(0, flw(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
676 gs
.dr_write32(0, fld(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
679 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
680 gs
.dr_write32(1, csrw(S0
, reg
- REG_CSR0
));
682 if (reg
== REG_CSR0
+ CSR_SPTBR
) {
684 gs
.sptbr_valid
= true;
686 } else if (reg
== REG_PRIV
) {
687 gs
.dcsr
= set_field(gs
.dcsr
, DCSR_PRV
, value
);
690 gs
.send_packet("E02");
694 gs
.send_packet("OK");
703 class memory_read_op_t
: public operation_t
706 // Read length bytes from vaddr, storing the result into data.
707 // If data is NULL, send the result straight to gdb.
708 memory_read_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
709 unsigned char *data
=NULL
) :
710 operation_t(gdbserver
), vaddr(vaddr
), length(length
), data(data
) {};
712 bool perform_step(unsigned int step
)
715 // address goes in S0
716 paddr
= gs
.translate(vaddr
);
717 access_size
= gs
.find_access_size(paddr
, length
);
719 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
720 switch (access_size
) {
722 gs
.dr_write32(1, lb(S1
, S0
, 0));
725 gs
.dr_write32(1, lh(S1
, S0
, 0));
728 gs
.dr_write32(1, lw(S1
, S0
, 0));
731 gs
.dr_write32(1, ld(S1
, S0
, 0));
734 gs
.dr_write_store(2, S1
, SLOT_DATA1
);
736 gs
.dr_write(SLOT_DATA0
, paddr
);
746 reg_t value
= gs
.dr_read(SLOT_DATA1
);
747 for (unsigned int i
= 0; i
< access_size
; i
++) {
749 *(data
++) = value
& 0xff;
750 D(fprintf(stderr
, "%02x", (unsigned int) (value
& 0xff)));
752 sprintf(buffer
, "%02x", (unsigned int) (value
& 0xff));
758 D(fprintf(stderr
, "\n"));
760 length
-= access_size
;
761 paddr
+= access_size
;
769 gs
.dr_write(SLOT_DATA0
, paddr
);
780 unsigned int access_size
;
783 class memory_write_op_t
: public operation_t
786 memory_write_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
787 const unsigned char *data
) :
788 operation_t(gdbserver
), vaddr(vaddr
), offset(0), length(length
), data(data
) {};
790 ~memory_write_op_t() {
794 bool perform_step(unsigned int step
)
796 reg_t paddr
= gs
.translate(vaddr
);
798 unsigned int data_offset
;
801 data_offset
= slot_offset32
[SLOT_DATA1
];
804 data_offset
= slot_offset64
[SLOT_DATA1
];
807 data_offset
= slot_offset128
[SLOT_DATA1
];
814 access_size
= gs
.find_access_size(paddr
, length
);
816 D(fprintf(stderr
, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr
, paddr
,
818 for (unsigned int i
= 0; i
< length
; i
++) {
819 D(fprintf(stderr
, "%02x", data
[i
]));
821 D(fprintf(stderr
, "\n"));
823 // address goes in S0
824 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
825 switch (access_size
) {
827 gs
.dr_write32(1, lb(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
828 gs
.dr_write32(2, sb(S1
, S0
, 0));
829 gs
.dr_write32(data_offset
, data
[0]);
832 gs
.dr_write32(1, lh(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
833 gs
.dr_write32(2, sh(S1
, S0
, 0));
834 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8));
837 gs
.dr_write32(1, lw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
838 gs
.dr_write32(2, sw(S1
, S0
, 0));
839 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8) |
840 (data
[2] << 16) | (data
[3] << 24));
843 gs
.dr_write32(1, ld(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
844 gs
.dr_write32(2, sd(S1
, S0
, 0));
845 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8) |
846 (data
[2] << 16) | (data
[3] << 24));
847 gs
.dr_write32(data_offset
+1, data
[4] | (data
[5] << 8) |
848 (data
[6] << 16) | (data
[7] << 24));
851 fprintf(stderr
, "gdbserver error: write %d bytes to 0x%lx -> 0x%lx; "
852 "access_size=%d\n", length
, vaddr
, paddr
, access_size
);
853 gs
.send_packet("E12");
857 gs
.dr_write(SLOT_DATA0
, paddr
);
863 if (gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1)) {
864 fprintf(stderr
, "Exception happened while writing to 0x%lx -> 0x%lx\n",
868 offset
+= access_size
;
869 if (offset
>= length
) {
870 gs
.send_packet("OK");
873 const unsigned char *d
= data
+ offset
;
874 switch (access_size
) {
876 gs
.dr_write32(data_offset
, d
[0]);
879 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8));
882 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8) |
883 (d
[2] << 16) | (d
[3] << 24));
886 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8) |
887 (d
[2] << 16) | (d
[3] << 24));
888 gs
.dr_write32(data_offset
+1, d
[4] | (d
[5] << 8) |
889 (d
[6] << 16) | (d
[7] << 24));
892 gs
.send_packet("E13");
895 gs
.dr_write(SLOT_DATA0
, paddr
+ offset
);
905 unsigned int access_size
;
906 const unsigned char *data
;
909 class collect_translation_info_op_t
: public operation_t
912 // Read sufficient information from the target into gdbserver structures so
913 // that it's possible to translate vaddr, vaddr+length, and all addresses
914 // in between to physical addresses.
915 collect_translation_info_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, size_t length
) :
916 operation_t(gdbserver
), state(STATE_START
), vaddr(vaddr
), length(length
) {};
918 bool perform_step(unsigned int step
)
920 unsigned int vm
= gs
.virtual_memory();
925 // Nothing to be done.
947 sprintf(buf
, "VM mode %d is not supported by gdbserver.cc.", vm
);
949 return true; // die doesn't return, but gcc doesn't know that.
954 // Perform any reads from the just-completed action.
958 case STATE_READ_SPTBR
:
959 gs
.sptbr
= gs
.dr_read(SLOT_DATA0
);
960 gs
.sptbr_valid
= true;
964 gs
.pte_cache
[pte_addr
] = gs
.dr_read32(4);
966 gs
.pte_cache
[pte_addr
] = ((uint64_t) gs
.dr_read32(5) << 32) |
969 D(fprintf(stderr
, "pte_cache[0x%lx] = 0x%lx\n", pte_addr
, gs
.pte_cache
[pte_addr
]));
973 // Set up the next action.
974 // We only get here for VM_SV32/39/38.
976 if (!gs
.sptbr_valid
) {
977 state
= STATE_READ_SPTBR
;
978 gs
.dr_write32(0, csrr(S0
, CSR_SPTBR
));
979 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
985 reg_t base
= gs
.sptbr
<< PGSHIFT
;
986 int ptshift
= (levels
- 1) * ptidxbits
;
987 for (unsigned int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
988 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
990 pte_addr
= base
+ idx
* ptesize
;
991 auto it
= gs
.pte_cache
.find(pte_addr
);
992 if (it
== gs
.pte_cache
.end()) {
993 state
= STATE_READ_PTE
;
995 gs
.dr_write32(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
996 gs
.dr_write32(1, lw(S1
, S0
, 0));
997 gs
.dr_write32(2, sw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
999 assert(gs
.xlen
>= 64);
1000 gs
.dr_write32(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1001 gs
.dr_write32(1, ld(S1
, S0
, 0));
1002 gs
.dr_write32(2, sd(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1004 gs
.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*3))));
1005 gs
.dr_write32(4, pte_addr
);
1006 gs
.dr_write32(5, pte_addr
>> 32);
1007 gs
.set_interrupt(0);
1011 reg_t pte
= gs
.pte_cache
[pte_addr
];
1012 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
1014 if (PTE_TABLE(pte
)) { // next level of page table
1015 base
= ppn
<< PGSHIFT
;
1017 // We've collected all the data required for the translation.
1022 "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%lx\n",
1035 unsigned int levels
;
1036 unsigned int ptidxbits
;
1037 unsigned int ptesize
;
1041 class hardware_breakpoint_insert_op_t
: public operation_t
1044 hardware_breakpoint_insert_op_t(gdbserver_t
& gdbserver
,
1045 hardware_breakpoint_t bp
) :
1046 operation_t(gdbserver
), state(STATE_START
), bp(bp
) {};
1048 void write_new_index_program()
1050 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1051 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1052 gs
.dr_write32(2, csrr(S0
, CSR_TSELECT
));
1053 gs
.dr_write_store(3, S0
, SLOT_DATA1
);
1054 gs
.dr_write_jump(4);
1055 gs
.dr_write(SLOT_DATA1
, bp
.index
);
1058 bool perform_step(unsigned int step
)
1063 write_new_index_program();
1064 state
= STATE_CHECK_INDEX
;
1067 case STATE_CHECK_INDEX
:
1068 if (gs
.dr_read(SLOT_DATA1
) != bp
.index
) {
1069 // We've exhausted breakpoints without finding an appropriate one.
1070 gs
.send_packet("E58");
1074 gs
.dr_write32(0, csrr(S0
, CSR_TDATA1
));
1075 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1076 gs
.dr_write_jump(2);
1077 state
= STATE_CHECK_MCONTROL
;
1080 case STATE_CHECK_MCONTROL
:
1082 reg_t mcontrol
= gs
.dr_read(SLOT_DATA0
);
1083 unsigned int type
= mcontrol
>> (gs
.xlen
- 4);
1085 // We've exhausted breakpoints without finding an appropriate one.
1086 gs
.send_packet("E58");
1091 !get_field(mcontrol
, MCONTROL_EXECUTE
) &&
1092 !get_field(mcontrol
, MCONTROL_LOAD
) &&
1093 !get_field(mcontrol
, MCONTROL_STORE
)) {
1094 // Found an unused trigger.
1095 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1096 gs
.dr_write32(1, csrw(S0
, CSR_TDATA1
));
1097 gs
.dr_write_jump(2);
1098 mcontrol
= set_field(0, MCONTROL_ACTION
, MCONTROL_ACTION_DEBUG_MODE
);
1099 mcontrol
= set_field(mcontrol
, MCONTROL_DMODE(gs
.xlen
), 1);
1100 mcontrol
= set_field(mcontrol
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
1101 mcontrol
= set_field(mcontrol
, MCONTROL_M
, 1);
1102 mcontrol
= set_field(mcontrol
, MCONTROL_H
, 1);
1103 mcontrol
= set_field(mcontrol
, MCONTROL_S
, 1);
1104 mcontrol
= set_field(mcontrol
, MCONTROL_U
, 1);
1105 mcontrol
= set_field(mcontrol
, MCONTROL_EXECUTE
, bp
.execute
);
1106 mcontrol
= set_field(mcontrol
, MCONTROL_LOAD
, bp
.load
);
1107 mcontrol
= set_field(mcontrol
, MCONTROL_STORE
, bp
.store
);
1108 // For store triggers it's nicer to fire just before the
1109 // instruction than just after. However, gdb doesn't clear the
1110 // breakpoints and step before resuming from a store trigger.
1111 // That means that without extra code, you'll keep hitting the
1112 // same watchpoint over and over again. That's not useful at all.
1113 // Instead of fixing this the right way, just set timing=1 for
1115 if (bp
.load
|| bp
.store
)
1116 mcontrol
= set_field(mcontrol
, MCONTROL_TIMING
, 1);
1118 gs
.dr_write(SLOT_DATA1
, mcontrol
);
1119 state
= STATE_WRITE_ADDRESS
;
1122 write_new_index_program();
1123 state
= STATE_CHECK_INDEX
;
1128 case STATE_WRITE_ADDRESS
:
1130 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1131 gs
.dr_write32(1, csrw(S0
, CSR_TDATA2
));
1132 gs
.dr_write_jump(2);
1133 gs
.dr_write(SLOT_DATA1
, bp
.vaddr
);
1134 gs
.set_interrupt(0);
1135 gs
.send_packet("OK");
1137 gs
.hardware_breakpoints
.insert(bp
);
1143 gs
.set_interrupt(0);
1151 STATE_CHECK_MCONTROL
,
1154 hardware_breakpoint_t bp
;
1157 class maybe_save_tselect_op_t
: public operation_t
1160 maybe_save_tselect_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1161 bool perform_step(unsigned int step
) {
1162 if (gs
.tselect_valid
)
1167 gs
.dr_write32(0, csrr(S0
, CSR_TDATA1
));
1168 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1169 gs
.dr_write_jump(2);
1170 gs
.set_interrupt(0);
1173 gs
.tselect
= gs
.dr_read(SLOT_DATA0
);
1174 gs
.tselect_valid
= true;
1181 class maybe_restore_tselect_op_t
: public operation_t
1184 maybe_restore_tselect_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1185 bool perform_step(unsigned int step
) {
1186 if (gs
.tselect_valid
) {
1187 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1188 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1189 gs
.dr_write_jump(2);
1190 gs
.dr_write(SLOT_DATA1
, gs
.tselect
);
1196 class hardware_breakpoint_remove_op_t
: public operation_t
1199 hardware_breakpoint_remove_op_t(gdbserver_t
& gdbserver
,
1200 hardware_breakpoint_t bp
) :
1201 operation_t(gdbserver
), bp(bp
) {};
1203 bool perform_step(unsigned int step
) {
1204 gs
.dr_write32(0, addi(S0
, ZERO
, bp
.index
));
1205 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1206 gs
.dr_write32(2, csrw(ZERO
, CSR_TDATA1
));
1207 gs
.dr_write_jump(3);
1208 gs
.set_interrupt(0);
1213 hardware_breakpoint_t bp
;
1216 ////////////////////////////// gdbserver itself
1218 gdbserver_t::gdbserver_t(uint16_t port
, sim_t
*sim
) :
1222 recv_buf(64 * 1024), send_buf(64 * 1024)
1224 socket_fd
= socket(AF_INET
, SOCK_STREAM
, 0);
1225 if (socket_fd
== -1) {
1226 fprintf(stderr
, "failed to make socket: %s (%d)\n", strerror(errno
), errno
);
1230 fcntl(socket_fd
, F_SETFL
, O_NONBLOCK
);
1232 if (setsockopt(socket_fd
, SOL_SOCKET
, SO_REUSEADDR
, &reuseaddr
,
1233 sizeof(int)) == -1) {
1234 fprintf(stderr
, "failed setsockopt: %s (%d)\n", strerror(errno
), errno
);
1238 struct sockaddr_in addr
;
1239 memset(&addr
, 0, sizeof(addr
));
1240 addr
.sin_family
= AF_INET
;
1241 addr
.sin_addr
.s_addr
= INADDR_ANY
;
1242 addr
.sin_port
= htons(port
);
1244 if (bind(socket_fd
, (struct sockaddr
*) &addr
, sizeof(addr
)) == -1) {
1245 fprintf(stderr
, "failed to bind socket: %s (%d)\n", strerror(errno
), errno
);
1249 if (listen(socket_fd
, 1) == -1) {
1250 fprintf(stderr
, "failed to listen on socket: %s (%d)\n", strerror(errno
), errno
);
1255 unsigned int gdbserver_t::find_access_size(reg_t address
, int length
)
1257 reg_t composite
= address
| length
;
1258 if ((composite
& 0x7) == 0 && xlen
>= 64)
1260 if ((composite
& 0x3) == 0)
1265 reg_t
gdbserver_t::translate(reg_t vaddr
)
1267 unsigned int vm
= virtual_memory();
1268 unsigned int levels
, ptidxbits
, ptesize
;
1293 sprintf(buf
, "VM mode %d is not supported by gdbserver.cc.", vm
);
1295 return true; // die doesn't return, but gcc doesn't know that.
1299 // Handle page tables here. There's a bunch of duplicated code with
1300 // collect_translation_info_op_t. :-(
1301 reg_t base
= sptbr
<< PGSHIFT
;
1302 int ptshift
= (levels
- 1) * ptidxbits
;
1303 for (unsigned int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
1304 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
1306 reg_t pte_addr
= base
+ idx
* ptesize
;
1307 auto it
= pte_cache
.find(pte_addr
);
1308 if (it
== pte_cache
.end()) {
1309 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%lx without first "
1310 "collecting the relevant PTEs.\n", vaddr
);
1311 die("gdbserver_t::translate()");
1314 reg_t pte
= pte_cache
[pte_addr
];
1315 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
1317 if (PTE_TABLE(pte
)) { // next level of page table
1318 base
= ppn
<< PGSHIFT
;
1320 // We've collected all the data required for the translation.
1321 reg_t vpn
= vaddr
>> PGSHIFT
;
1322 reg_t paddr
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
1323 paddr
+= vaddr
& (PGSIZE
-1);
1324 D(fprintf(stderr
, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr
, paddr
));
1329 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%lx but the relevant "
1330 "PTEs are invalid.\n", vaddr
);
1331 // TODO: Is it better to throw an exception here?
1335 unsigned int gdbserver_t::privilege_mode()
1337 unsigned int mode
= get_field(dcsr
, DCSR_PRV
);
1338 if (get_field(mstatus
, MSTATUS_MPRV
))
1339 mode
= get_field(mstatus
, MSTATUS_MPP
);
1343 unsigned int gdbserver_t::virtual_memory()
1345 unsigned int mode
= privilege_mode();
1348 return get_field(mstatus
, MSTATUS_VM
);
1351 void gdbserver_t::dr_write32(unsigned int index
, uint32_t value
)
1353 sim
->debug_module
.ram_write32(index
, value
);
1356 void gdbserver_t::dr_write64(unsigned int index
, uint64_t value
)
1358 dr_write32(index
, value
);
1359 dr_write32(index
+1, value
>> 32);
1362 void gdbserver_t::dr_write(enum slot slot
, uint64_t value
)
1366 dr_write32(slot_offset32
[slot
], value
);
1369 dr_write64(slot_offset64
[slot
], value
);
1377 void gdbserver_t::dr_write_jump(unsigned int index
)
1379 dr_write32(index
, jal(0,
1380 (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*index
))));
1383 void gdbserver_t::dr_write_store(unsigned int index
, unsigned int reg
, enum slot slot
)
1385 assert(slot
!= SLOT_INST0
|| index
> 2);
1386 assert(slot
!= SLOT_DATA0
|| index
< 4 || index
> 6);
1387 assert(slot
!= SLOT_DATA1
|| index
< 5 || index
> 10);
1388 assert(slot
!= SLOT_DATA_LAST
|| index
< 6 || index
> 14);
1391 return dr_write32(index
,
1392 sw(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset32
[slot
]));
1394 return dr_write32(index
,
1395 sd(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset64
[slot
]));
1397 return dr_write32(index
,
1398 sq(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset128
[slot
]));
1400 fprintf(stderr
, "xlen is %d!\n", xlen
);
1405 void gdbserver_t::dr_write_load(unsigned int index
, unsigned int reg
, enum slot slot
)
1409 return dr_write32(index
,
1410 lw(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset32
[slot
]));
1412 return dr_write32(index
,
1413 ld(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset64
[slot
]));
1415 return dr_write32(index
,
1416 lq(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset128
[slot
]));
1418 fprintf(stderr
, "xlen is %d!\n", xlen
);
1423 uint32_t gdbserver_t::dr_read32(unsigned int index
)
1425 uint32_t value
= sim
->debug_module
.ram_read32(index
);
1426 D(fprintf(stderr
, "read32(%d) -> 0x%x\n", index
, value
));
1430 uint64_t gdbserver_t::dr_read64(unsigned int index
)
1432 return ((uint64_t) dr_read32(index
+1) << 32) | dr_read32(index
);
1435 uint64_t gdbserver_t::dr_read(enum slot slot
)
1439 return dr_read32(slot_offset32
[slot
]);
1441 return dr_read64(slot_offset64
[slot
]);
1449 void gdbserver_t::add_operation(operation_t
* operation
)
1451 operation_queue
.push(operation
);
1454 void gdbserver_t::accept()
1456 client_fd
= ::accept(socket_fd
, NULL
, NULL
);
1457 if (client_fd
== -1) {
1458 if (errno
== EAGAIN
) {
1459 // No client waiting to connect right now.
1461 fprintf(stderr
, "failed to accept on socket: %s (%d)\n", strerror(errno
),
1466 fcntl(client_fd
, F_SETFL
, O_NONBLOCK
);
1469 extended_mode
= false;
1471 // gdb wants the core to be halted when it attaches.
1472 add_operation(new halt_op_t(*this));
1476 void gdbserver_t::read()
1478 // Reading from a non-blocking socket still blocks if there is no data
1481 size_t count
= recv_buf
.contiguous_empty_size();
1483 ssize_t bytes
= ::read(client_fd
, recv_buf
.contiguous_empty(), count
);
1485 if (errno
== EAGAIN
) {
1486 // We'll try again the next call.
1488 fprintf(stderr
, "failed to read on socket: %s (%d)\n", strerror(errno
), errno
);
1491 } else if (bytes
== 0) {
1492 // The remote disconnected.
1494 processor_t
*p
= sim
->get_core(0);
1495 // TODO p->set_halted(false, HR_NONE);
1499 recv_buf
.data_added(bytes
);
1503 void gdbserver_t::write()
1505 if (send_buf
.empty())
1508 while (!send_buf
.empty()) {
1509 unsigned int count
= send_buf
.contiguous_data_size();
1511 ssize_t bytes
= ::write(client_fd
, send_buf
.contiguous_data(), count
);
1513 fprintf(stderr
, "failed to write to socket: %s (%d)\n", strerror(errno
), errno
);
1515 } else if (bytes
== 0) {
1516 // Client can't take any more data right now.
1519 D(fprintf(stderr
, "wrote %ld bytes: ", bytes
));
1520 for (unsigned int i
= 0; i
< bytes
; i
++) {
1521 D(fprintf(stderr
, "%c", send_buf
[i
]));
1523 D(fprintf(stderr
, "\n"));
1524 send_buf
.consume(bytes
);
1529 void print_packet(const std::vector
<uint8_t> &packet
)
1531 for (uint8_t c
: packet
) {
1532 if (c
>= ' ' and c
<= '~')
1533 fprintf(stderr
, "%c", c
);
1535 fprintf(stderr
, "\\x%02x", c
);
1537 fprintf(stderr
, "\n");
1540 uint8_t compute_checksum(const std::vector
<uint8_t> &packet
)
1542 uint8_t checksum
= 0;
1543 for (auto i
= packet
.begin() + 1; i
!= packet
.end() - 3; i
++ ) {
1549 uint8_t character_hex_value(uint8_t character
)
1551 if (character
>= '0' && character
<= '9')
1552 return character
- '0';
1553 if (character
>= 'a' && character
<= 'f')
1554 return 10 + character
- 'a';
1555 if (character
>= 'A' && character
<= 'F')
1556 return 10 + character
- 'A';
1560 uint8_t extract_checksum(const std::vector
<uint8_t> &packet
)
1562 return character_hex_value(*(packet
.end() - 1)) +
1563 16 * character_hex_value(*(packet
.end() - 2));
1566 void gdbserver_t::process_requests()
1568 // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1570 while (!recv_buf
.empty()) {
1571 std::vector
<uint8_t> packet
;
1572 for (unsigned int i
= 0; i
< recv_buf
.size(); i
++) {
1573 uint8_t b
= recv_buf
[i
];
1575 if (packet
.empty() && expect_ack
&& b
== '+') {
1576 recv_buf
.consume(1);
1580 if (packet
.empty() && b
== 3) {
1581 D(fprintf(stderr
, "Received interrupt\n"));
1582 recv_buf
.consume(1);
1588 // Start of new packet.
1589 if (!packet
.empty()) {
1590 fprintf(stderr
, "Received malformed %ld-byte packet from debug client: ",
1592 print_packet(packet
);
1593 recv_buf
.consume(i
);
1598 packet
.push_back(b
);
1600 // Packets consist of $<packet-data>#<checksum>
1601 // where <checksum> is
1602 if (packet
.size() >= 4 &&
1603 packet
[packet
.size()-3] == '#') {
1604 handle_packet(packet
);
1605 recv_buf
.consume(i
+1);
1609 // There's a partial packet in the buffer. Wait until we get more data to
1611 if (packet
.size()) {
1617 void gdbserver_t::handle_halt_reason(const std::vector
<uint8_t> &packet
)
1622 void gdbserver_t::handle_general_registers_read(const std::vector
<uint8_t> &packet
)
1624 add_operation(new general_registers_read_op_t(*this));
1627 void gdbserver_t::set_interrupt(uint32_t hartid
) {
1628 sim
->debug_module
.set_interrupt(hartid
);
1631 // First byte is the most-significant one.
1632 // Eg. "08675309" becomes 0x08675309.
1633 uint64_t consume_hex_number(std::vector
<uint8_t>::const_iterator
&iter
,
1634 std::vector
<uint8_t>::const_iterator end
)
1638 while (iter
!= end
) {
1640 uint64_t c_value
= character_hex_value(c
);
1650 // First byte is the least-significant one.
1651 // Eg. "08675309" becomes 0x09536708
1652 uint64_t consume_hex_number_le(std::vector
<uint8_t>::const_iterator
&iter
,
1653 std::vector
<uint8_t>::const_iterator end
)
1656 unsigned int shift
= 4;
1658 while (iter
!= end
) {
1660 uint64_t c_value
= character_hex_value(c
);
1664 value
|= c_value
<< shift
;
1665 if ((shift
% 8) == 0)
1673 void consume_string(std::string
&str
, std::vector
<uint8_t>::const_iterator
&iter
,
1674 std::vector
<uint8_t>::const_iterator end
, uint8_t separator
)
1676 while (iter
!= end
&& *iter
!= separator
) {
1677 str
.append(1, (char) *iter
);
1682 void gdbserver_t::handle_register_read(const std::vector
<uint8_t> &packet
)
1686 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1687 unsigned int n
= consume_hex_number(iter
, packet
.end());
1689 return send_packet("E01");
1691 add_operation(new register_read_op_t(*this, n
));
1694 void gdbserver_t::handle_register_write(const std::vector
<uint8_t> &packet
)
1698 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1699 unsigned int n
= consume_hex_number(iter
, packet
.end());
1701 return send_packet("E05");
1704 reg_t value
= consume_hex_number_le(iter
, packet
.end());
1706 return send_packet("E06");
1708 processor_t
*p
= sim
->get_core(0);
1710 add_operation(new register_write_op_t(*this, n
, value
));
1712 return send_packet("OK");
1715 void gdbserver_t::handle_memory_read(const std::vector
<uint8_t> &packet
)
1718 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1719 reg_t address
= consume_hex_number(iter
, packet
.end());
1721 return send_packet("E10");
1723 reg_t length
= consume_hex_number(iter
, packet
.end());
1725 return send_packet("E11");
1727 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1728 add_operation(new memory_read_op_t(*this, address
, length
));
1731 void gdbserver_t::handle_memory_binary_write(const std::vector
<uint8_t> &packet
)
1733 // X addr,length:XX...
1734 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1735 reg_t address
= consume_hex_number(iter
, packet
.end());
1737 return send_packet("E20");
1739 reg_t length
= consume_hex_number(iter
, packet
.end());
1741 return send_packet("E21");
1745 return send_packet("OK");
1748 unsigned char *data
= new unsigned char[length
];
1749 for (unsigned int i
= 0; i
< length
; i
++) {
1750 if (iter
== packet
.end()) {
1751 return send_packet("E22");
1756 // The binary data representation uses 7d (ascii ‘}’) as an escape
1757 // character. Any escaped byte is transmitted as the escape character
1758 // followed by the original character XORed with 0x20. For example, the
1759 // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1760 // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1762 if (iter
== packet
.end()) {
1763 return send_packet("E23");
1771 return send_packet("E4b"); // EOVERFLOW
1773 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1774 add_operation(new memory_write_op_t(*this, address
, length
, data
));
1777 void gdbserver_t::handle_continue(const std::vector
<uint8_t> &packet
)
1780 processor_t
*p
= sim
->get_core(0);
1781 if (packet
[2] != '#') {
1782 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1783 dpc
= consume_hex_number(iter
, packet
.end());
1785 return send_packet("E30");
1788 add_operation(new maybe_restore_tselect_op_t(*this));
1789 add_operation(new continue_op_t(*this, false));
1792 void gdbserver_t::handle_step(const std::vector
<uint8_t> &packet
)
1795 if (packet
[2] != '#') {
1796 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1798 //p->state.pc = consume_hex_number(iter, packet.end());
1800 return send_packet("E40");
1803 add_operation(new maybe_restore_tselect_op_t(*this));
1804 add_operation(new continue_op_t(*this, true));
1807 void gdbserver_t::handle_kill(const std::vector
<uint8_t> &packet
)
1810 // The exact effect of this packet is not specified.
1811 // Looks like OpenOCD disconnects?
1815 void gdbserver_t::handle_extended(const std::vector
<uint8_t> &packet
)
1817 // Enable extended mode. In extended mode, the remote server is made
1818 // persistent. The ‘R’ packet is used to restart the program being debugged.
1820 extended_mode
= true;
1823 void gdbserver_t::software_breakpoint_insert(reg_t vaddr
, unsigned int size
)
1825 fence_i_required
= true;
1826 add_operation(new collect_translation_info_op_t(*this, vaddr
, size
));
1827 unsigned char* inst
= new unsigned char[4];
1829 inst
[0] = C_EBREAK
& 0xff;
1830 inst
[1] = (C_EBREAK
>> 8) & 0xff;
1832 inst
[0] = EBREAK
& 0xff;
1833 inst
[1] = (EBREAK
>> 8) & 0xff;
1834 inst
[2] = (EBREAK
>> 16) & 0xff;
1835 inst
[3] = (EBREAK
>> 24) & 0xff;
1838 software_breakpoint_t bp
= {
1842 software_breakpoints
[vaddr
] = bp
;
1843 add_operation(new memory_read_op_t(*this, bp
.vaddr
, bp
.size
,
1844 software_breakpoints
[bp
.vaddr
].instruction
));
1845 add_operation(new memory_write_op_t(*this, bp
.vaddr
, bp
.size
, inst
));
1848 void gdbserver_t::software_breakpoint_remove(reg_t vaddr
, unsigned int size
)
1850 fence_i_required
= true;
1851 add_operation(new collect_translation_info_op_t(*this, vaddr
, size
));
1853 software_breakpoint_t found_bp
= software_breakpoints
[vaddr
];
1854 unsigned char* instruction
= new unsigned char[4];
1855 memcpy(instruction
, found_bp
.instruction
, 4);
1856 add_operation(new memory_write_op_t(*this, found_bp
.vaddr
,
1857 found_bp
.size
, instruction
));
1858 software_breakpoints
.erase(vaddr
);
1861 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t
&bp
)
1863 add_operation(new maybe_save_tselect_op_t(*this));
1864 add_operation(new hardware_breakpoint_insert_op_t(*this, bp
));
1867 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t
&bp
)
1869 add_operation(new maybe_save_tselect_op_t(*this));
1870 hardware_breakpoint_t found
= *hardware_breakpoints
.find(bp
);
1871 add_operation(new hardware_breakpoint_remove_op_t(*this, found
));
1874 void gdbserver_t::handle_breakpoint(const std::vector
<uint8_t> &packet
)
1876 // insert: Z type,addr,length
1877 // remove: z type,addr,length
1879 // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1880 // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1881 // length is in bytes. For a software breakpoint, length specifies the size
1882 // of the instruction to be patched. For hardware breakpoints and watchpoints
1883 // length specifies the memory region to be monitored. To avoid potential
1884 // problems with duplicate packets, the operations should be implemented in
1885 // an idempotent way.
1887 bool insert
= (packet
[1] == 'Z');
1888 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1889 gdb_breakpoint_type_t type
= static_cast<gdb_breakpoint_type_t
>(
1890 consume_hex_number(iter
, packet
.end()));
1892 return send_packet("E50");
1894 reg_t address
= consume_hex_number(iter
, packet
.end());
1896 return send_packet("E51");
1898 unsigned int size
= consume_hex_number(iter
, packet
.end());
1899 // There may be more options after a ; here, but we don't support that.
1901 return send_packet("E52");
1905 if (size
!= 2 && size
!= 4) {
1906 return send_packet("E53");
1909 software_breakpoint_insert(address
, size
);
1911 software_breakpoint_remove(address
, size
);
1920 hardware_breakpoint_t bp
= {
1924 bp
.load
= (type
== GB_READ
|| type
== GB_ACCESS
);
1925 bp
.store
= (type
== GB_WRITE
|| type
== GB_ACCESS
);
1926 bp
.execute
= (type
== GB_HARDWARE
|| type
== GB_ACCESS
);
1928 hardware_breakpoint_insert(bp
);
1929 // Insert might fail if there's no space, so the insert operation will
1930 // send its own OK (or not).
1933 hardware_breakpoint_remove(bp
);
1939 return send_packet("E56");
1942 return send_packet("OK");
1945 void gdbserver_t::handle_query(const std::vector
<uint8_t> &packet
)
1948 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1950 consume_string(name
, iter
, packet
.end(), ':');
1951 if (iter
!= packet
.end())
1953 if (name
== "Supported") {
1955 while (iter
!= packet
.end()) {
1956 std::string feature
;
1957 consume_string(feature
, iter
, packet
.end(), ';');
1958 if (iter
!= packet
.end())
1960 if (feature
== "swbreak+") {
1964 send("PacketSize=131072;");
1965 return end_packet();
1968 D(fprintf(stderr
, "Unsupported query %s\n", name
.c_str()));
1969 return send_packet("");
1972 void gdbserver_t::handle_packet(const std::vector
<uint8_t> &packet
)
1974 if (compute_checksum(packet
) != extract_checksum(packet
)) {
1975 fprintf(stderr
, "Received %ld-byte packet with invalid checksum\n", packet
.size());
1976 fprintf(stderr
, "Computed checksum: %x\n", compute_checksum(packet
));
1977 print_packet(packet
);
1982 D(fprintf(stderr
, "Received %ld-byte packet from debug client: ", packet
.size()));
1983 D(print_packet(packet
));
1986 switch (packet
[1]) {
1988 return handle_extended(packet
);
1990 return handle_halt_reason(packet
);
1992 return handle_general_registers_read(packet
);
1994 // return handle_kill(packet);
1996 return handle_memory_read(packet
);
1998 // return handle_memory_write(packet);
2000 return handle_memory_binary_write(packet
);
2002 return handle_register_read(packet
);
2004 return handle_register_write(packet
);
2006 return handle_continue(packet
);
2008 return handle_step(packet
);
2011 return handle_breakpoint(packet
);
2014 return handle_query(packet
);
2018 D(fprintf(stderr
, "** Unsupported packet: "));
2019 D(print_packet(packet
));
2023 void gdbserver_t::handle_interrupt()
2025 processor_t
*p
= sim
->get_core(0);
2026 add_operation(new halt_op_t(*this, true));
2029 void gdbserver_t::handle()
2031 if (client_fd
> 0) {
2032 processor_t
*p
= sim
->get_core(0);
2034 bool interrupt
= sim
->debug_module
.get_interrupt(0);
2036 if (!interrupt
&& !operation_queue
.empty()) {
2037 operation_t
*operation
= operation_queue
.front();
2038 if (operation
->step()) {
2039 operation_queue
.pop();
2044 bool halt_notification
= sim
->debug_module
.get_halt_notification(0);
2045 if (halt_notification
) {
2046 sim
->debug_module
.clear_halt_notification(0);
2047 add_operation(new halt_op_t(*this, true));
2057 if (operation_queue
.empty()) {
2058 this->process_requests();
2062 void gdbserver_t::send(const char* msg
)
2064 unsigned int length
= strlen(msg
);
2065 for (const char *c
= msg
; *c
; c
++)
2066 running_checksum
+= *c
;
2067 send_buf
.append((const uint8_t *) msg
, length
);
2070 void gdbserver_t::send(uint64_t value
)
2073 for (unsigned int i
= 0; i
< 8; i
++) {
2074 sprintf(buffer
, "%02x", (int) (value
& 0xff));
2080 void gdbserver_t::send(uint32_t value
)
2083 for (unsigned int i
= 0; i
< 4; i
++) {
2084 sprintf(buffer
, "%02x", (int) (value
& 0xff));
2090 void gdbserver_t::send(uint8_t value
)
2093 sprintf(buffer
, "%02x", (int) value
);
2097 void gdbserver_t::send_packet(const char* data
)
2105 void gdbserver_t::start_packet()
2108 running_checksum
= 0;
2111 void gdbserver_t::end_packet(const char* data
)
2117 char checksum_string
[4];
2118 sprintf(checksum_string
, "#%02x", running_checksum
);
2119 send(checksum_string
);