6 #include <sys/socket.h>
18 #include "gdbserver.h"
21 #define C_EBREAK 0x9002
22 #define EBREAK 0x00100073
24 //////////////////////////////////////// Utility Functions
33 void die(const char* msg
)
35 fprintf(stderr
, "gdbserver code died: %s\n", msg
);
39 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
40 // its source tree. We must interpret the numbers the same here.
52 //////////////////////////////////////// Functions to generate RISC-V opcodes.
54 // TODO: Does this already exist somewhere?
57 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
58 // spec says it should be 2 and 3.
61 static uint32_t bits(uint32_t value
, unsigned int hi
, unsigned int lo
) {
62 return (value
>> lo
) & ((1 << (hi
+1-lo
)) - 1);
65 static uint32_t bit(uint32_t value
, unsigned int b
) {
66 return (value
>> b
) & 1;
69 static uint32_t jal(unsigned int rd
, uint32_t imm
) {
70 return (bit(imm
, 20) << 31) |
71 (bits(imm
, 10, 1) << 21) |
72 (bit(imm
, 11) << 20) |
73 (bits(imm
, 19, 12) << 12) |
78 static uint32_t csrsi(unsigned int csr
, uint16_t imm
) {
80 (bits(imm
, 4, 0) << 15) |
84 static uint32_t csrci(unsigned int csr
, uint16_t imm
) {
86 (bits(imm
, 4, 0) << 15) |
90 static uint32_t csrr(unsigned int rd
, unsigned int csr
) {
91 return (csr
<< 20) | (rd
<< 7) | MATCH_CSRRS
;
94 static uint32_t csrw(unsigned int source
, unsigned int csr
) {
95 return (csr
<< 20) | (source
<< 15) | MATCH_CSRRW
;
98 static uint32_t fence_i()
100 return MATCH_FENCE_I
;
103 static uint32_t sb(unsigned int src
, unsigned int base
, uint16_t offset
)
105 return (bits(offset
, 11, 5) << 25) |
108 (bits(offset
, 4, 0) << 7) |
112 static uint32_t sh(unsigned int src
, unsigned int base
, uint16_t offset
)
114 return (bits(offset
, 11, 5) << 25) |
117 (bits(offset
, 4, 0) << 7) |
121 static uint32_t sw(unsigned int src
, unsigned int base
, uint16_t offset
)
123 return (bits(offset
, 11, 5) << 25) |
126 (bits(offset
, 4, 0) << 7) |
130 static uint32_t sd(unsigned int src
, unsigned int base
, uint16_t offset
)
132 return (bits(offset
, 11, 5) << 25) |
133 (bits(src
, 4, 0) << 20) |
135 (bits(offset
, 4, 0) << 7) |
139 static uint32_t sq(unsigned int src
, unsigned int base
, uint16_t offset
)
142 return (bits(offset
, 11, 5) << 25) |
143 (bits(src
, 4, 0) << 20) |
145 (bits(offset
, 4, 0) << 7) |
152 static uint32_t lq(unsigned int rd
, unsigned int base
, uint16_t offset
)
155 return (bits(offset
, 11, 0) << 20) |
157 (bits(rd
, 4, 0) << 7) |
164 static uint32_t ld(unsigned int rd
, unsigned int base
, uint16_t offset
)
166 return (bits(offset
, 11, 0) << 20) |
168 (bits(rd
, 4, 0) << 7) |
172 static uint32_t lw(unsigned int rd
, unsigned int base
, uint16_t offset
)
174 return (bits(offset
, 11, 0) << 20) |
176 (bits(rd
, 4, 0) << 7) |
180 static uint32_t lh(unsigned int rd
, unsigned int base
, uint16_t offset
)
182 return (bits(offset
, 11, 0) << 20) |
184 (bits(rd
, 4, 0) << 7) |
188 static uint32_t lb(unsigned int rd
, unsigned int base
, uint16_t offset
)
190 return (bits(offset
, 11, 0) << 20) |
192 (bits(rd
, 4, 0) << 7) |
196 static uint32_t fsw(unsigned int src
, unsigned int base
, uint16_t offset
)
198 return (bits(offset
, 11, 5) << 25) |
199 (bits(src
, 4, 0) << 20) |
201 (bits(offset
, 4, 0) << 7) |
205 static uint32_t fsd(unsigned int src
, unsigned int base
, uint16_t offset
)
207 return (bits(offset
, 11, 5) << 25) |
208 (bits(src
, 4, 0) << 20) |
210 (bits(offset
, 4, 0) << 7) |
214 static uint32_t flw(unsigned int src
, unsigned int base
, uint16_t offset
)
216 return (bits(offset
, 11, 5) << 25) |
217 (bits(src
, 4, 0) << 20) |
219 (bits(offset
, 4, 0) << 7) |
223 static uint32_t fld(unsigned int src
, unsigned int base
, uint16_t offset
)
225 return (bits(offset
, 11, 5) << 25) |
226 (bits(src
, 4, 0) << 20) |
228 (bits(offset
, 4, 0) << 7) |
232 static uint32_t addi(unsigned int dest
, unsigned int src
, uint16_t imm
)
234 return (bits(imm
, 11, 0) << 20) |
240 static uint32_t ori(unsigned int dest
, unsigned int src
, uint16_t imm
)
242 return (bits(imm
, 11, 0) << 20) |
248 static uint32_t xori(unsigned int dest
, unsigned int src
, uint16_t imm
)
250 return (bits(imm
, 11, 0) << 20) |
256 static uint32_t srli(unsigned int dest
, unsigned int src
, uint8_t shamt
)
258 return (bits(shamt
, 4, 0) << 20) |
265 static uint32_t nop()
267 return addi(0, 0, 0);
270 template <typename T
>
271 unsigned int circular_buffer_t
<T
>::size() const
276 return end
+ capacity
- start
;
279 template <typename T
>
280 void circular_buffer_t
<T
>::consume(unsigned int bytes
)
282 start
= (start
+ bytes
) % capacity
;
285 template <typename T
>
286 unsigned int circular_buffer_t
<T
>::contiguous_empty_size() const
290 return capacity
- end
- 1;
292 return capacity
- end
;
294 return start
- end
- 1;
297 template <typename T
>
298 unsigned int circular_buffer_t
<T
>::contiguous_data_size() const
303 return capacity
- start
;
306 template <typename T
>
307 void circular_buffer_t
<T
>::data_added(unsigned int bytes
)
310 assert(end
<= capacity
);
315 template <typename T
>
316 void circular_buffer_t
<T
>::reset()
322 template <typename T
>
323 void circular_buffer_t
<T
>::append(const T
*src
, unsigned int count
)
325 unsigned int copy
= std::min(count
, contiguous_empty_size());
326 memcpy(contiguous_empty(), src
, copy
* sizeof(T
));
330 assert(count
< contiguous_empty_size());
331 memcpy(contiguous_empty(), src
, count
* sizeof(T
));
336 ////////////////////////////// Debug Operations
338 class halt_op_t
: public operation_t
341 halt_op_t(gdbserver_t
& gdbserver
, bool send_status
=false) :
342 operation_t(gdbserver
), send_status(send_status
),
345 void write_dpc_program() {
346 gs
.dr_write32(0, csrsi(CSR_DCSR
, DCSR_HALT
));
347 gs
.dr_write32(1, csrr(S0
, CSR_DPC
));
348 gs
.dr_write_store(2, S0
, SLOT_DATA0
);
353 bool perform_step(unsigned int step
) {
355 gs
.tselect_valid
= false;
358 gs
.dr_write32(0, xori(S1
, ZERO
, -1));
359 gs
.dr_write32(1, srli(S1
, S1
, 31));
360 // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
361 gs
.dr_write32(2, sw(S1
, ZERO
, DEBUG_RAM_START
));
362 gs
.dr_write32(3, srli(S1
, S1
, 31));
363 // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
364 gs
.dr_write32(4, sw(S1
, ZERO
, DEBUG_RAM_START
+ 4));
377 uint32_t word0
= gs
.dr_read32(0);
378 uint32_t word1
= gs
.dr_read32(1);
380 if (word0
== 1 && word1
== 0) {
382 } else if (word0
== 0xffffffff && word1
== 3) {
384 } else if (word0
== 0xffffffff && word1
== 0xffffffff) {
394 gs
.dpc
= gs
.dr_read(SLOT_DATA0
);
395 gs
.dr_write32(0, csrr(S0
, CSR_MSTATUS
));
396 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
403 gs
.mstatus
= gs
.dr_read(SLOT_DATA0
);
404 gs
.dr_write32(0, csrr(S0
, CSR_DCSR
));
405 gs
.dr_write32(1, sw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
412 gs
.dcsr
= gs
.dr_read32(4);
414 gs
.sptbr_valid
= false;
415 gs
.pte_cache
.clear();
418 switch (get_field(gs
.dcsr
, DCSR_CAUSE
)) {
419 case DCSR_CAUSE_NONE
:
420 fprintf(stderr
, "Internal error. Processor halted without reason.\n");
423 case DCSR_CAUSE_DEBUGINT
:
424 gs
.send_packet("S02"); // Pretend program received SIGINT.
427 case DCSR_CAUSE_HWBP
:
428 case DCSR_CAUSE_STEP
:
429 case DCSR_CAUSE_HALT
:
430 // There's no gdb code for this.
431 gs
.send_packet("T05");
433 case DCSR_CAUSE_SWBP
:
434 gs
.send_packet("T05swbreak:;");
456 class continue_op_t
: public operation_t
459 continue_op_t(gdbserver_t
& gdbserver
, bool single_step
) :
460 operation_t(gdbserver
), single_step(single_step
) {};
462 bool perform_step(unsigned int step
) {
463 D(fprintf(stderr
, "continue step %d\n", step
));
466 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
467 gs
.dr_write32(1, csrw(S0
, CSR_DPC
));
468 // TODO: Isn't there a fence.i in Debug ROM already?
469 if (gs
.fence_i_required
) {
470 gs
.dr_write32(2, fence_i());
472 gs
.fence_i_required
= false;
476 gs
.dr_write(SLOT_DATA0
, gs
.dpc
);
481 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
482 gs
.dr_write32(1, csrw(S0
, CSR_MSTATUS
));
484 gs
.dr_write(SLOT_DATA0
, gs
.mstatus
);
489 gs
.dr_write32(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+16));
490 gs
.dr_write32(1, csrw(S0
, CSR_DCSR
));
493 reg_t dcsr
= set_field(gs
.dcsr
, DCSR_HALT
, 0);
494 dcsr
= set_field(dcsr
, DCSR_STEP
, single_step
);
495 // Software breakpoints should go here.
496 dcsr
= set_field(dcsr
, DCSR_EBREAKM
, 1);
497 dcsr
= set_field(dcsr
, DCSR_EBREAKH
, 1);
498 dcsr
= set_field(dcsr
, DCSR_EBREAKS
, 1);
499 dcsr
= set_field(dcsr
, DCSR_EBREAKU
, 1);
500 gs
.dr_write32(4, dcsr
);
512 class general_registers_read_op_t
: public operation_t
514 // Register order that gdb expects is:
515 // "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
516 // "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
517 // "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
518 // "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
520 // Each byte of register data is described by two hex digits. The bytes with
521 // the register are transmitted in target byte order. The size of each
522 // register and their position within the ‘g’ packet are determined by the
523 // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
524 // gdbarch_register_name.
527 general_registers_read_op_t(gdbserver_t
& gdbserver
) :
528 operation_t(gdbserver
) {};
530 bool perform_step(unsigned int step
)
532 D(fprintf(stderr
, "register_read step %d\n", step
));
536 // x0 is always zero.
538 gs
.send((uint32_t) 0);
540 gs
.send((uint64_t) 0);
543 gs
.dr_write_store(0, 1, SLOT_DATA0
);
544 gs
.dr_write_store(1, 2, SLOT_DATA1
);
551 gs
.send((uint32_t) gs
.dr_read(SLOT_DATA0
));
553 gs
.send((uint64_t) gs
.dr_read(SLOT_DATA0
));
561 gs
.send((uint32_t) gs
.dr_read(SLOT_DATA1
));
563 gs
.send((uint64_t) gs
.dr_read(SLOT_DATA1
));
566 unsigned int current_reg
= 2 * step
+ 1;
568 if (current_reg
== S1
) {
569 gs
.dr_write_load(i
++, S1
, SLOT_DATA_LAST
);
571 gs
.dr_write_store(i
++, current_reg
, SLOT_DATA0
);
572 if (current_reg
+ 1 == S0
) {
573 gs
.dr_write32(i
++, csrr(S0
, CSR_DSCRATCH
));
576 gs
.dr_write_store(i
++, current_reg
+1, SLOT_DATA1
);
585 class register_read_op_t
: public operation_t
588 register_read_op_t(gdbserver_t
& gdbserver
, unsigned int reg
) :
589 operation_t(gdbserver
), reg(reg
) {};
591 bool perform_step(unsigned int step
)
595 if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
596 die("handle_register_read");
597 // send(p->state.XPR[reg - REG_XPR0]);
598 } else if (reg
== REG_PC
) {
601 gs
.send((uint32_t) gs
.dpc
);
607 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
608 // send(p->state.FPR[reg - REG_FPR0]);
610 gs
.dr_write32(0, fsw(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
612 gs
.dr_write32(0, fsd(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
615 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
616 gs
.dr_write32(0, csrr(S0
, reg
- REG_CSR0
));
617 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
619 // If we hit an exception reading the CSR, we'll end up returning ~0 as
620 // the register's value, which is what we want. (Right?)
621 gs
.dr_write(SLOT_DATA0
, ~(uint64_t) 0);
622 } else if (reg
== REG_PRIV
) {
624 gs
.send((uint8_t) get_field(gs
.dcsr
, DCSR_PRV
));
628 gs
.send_packet("E02");
637 gs
.send(gs
.dr_read32(4));
639 gs
.send(gs
.dr_read(SLOT_DATA0
));
651 class register_write_op_t
: public operation_t
654 register_write_op_t(gdbserver_t
& gdbserver
, unsigned int reg
, reg_t value
) :
655 operation_t(gdbserver
), reg(reg
), value(value
) {};
657 bool perform_step(unsigned int step
)
659 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
660 gs
.dr_write(SLOT_DATA0
, value
);
662 gs
.dr_write32(1, csrw(S0
, CSR_DSCRATCH
));
664 } else if (reg
== S1
) {
665 gs
.dr_write_store(1, S0
, SLOT_DATA_LAST
);
667 } else if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
668 gs
.dr_write32(1, addi(reg
, S0
, 0));
670 } else if (reg
== REG_PC
) {
673 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
675 gs
.dr_write32(0, flw(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
677 gs
.dr_write32(0, fld(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
680 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
681 gs
.dr_write32(1, csrw(S0
, reg
- REG_CSR0
));
683 if (reg
== REG_CSR0
+ CSR_SPTBR
) {
685 gs
.sptbr_valid
= true;
687 } else if (reg
== REG_PRIV
) {
688 gs
.dcsr
= set_field(gs
.dcsr
, DCSR_PRV
, value
);
691 gs
.send_packet("E02");
695 gs
.send_packet("OK");
704 class memory_read_op_t
: public operation_t
707 // Read length bytes from vaddr, storing the result into data.
708 // If data is NULL, send the result straight to gdb.
709 memory_read_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
710 unsigned char *data
=NULL
) :
711 operation_t(gdbserver
), vaddr(vaddr
), length(length
), data(data
), index(0)
713 buf
= new uint8_t[length
];
721 bool perform_step(unsigned int step
)
724 // address goes in S0
725 paddr
= gs
.translate(vaddr
);
726 access_size
= gs
.find_access_size(paddr
, length
);
728 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
729 switch (access_size
) {
731 gs
.dr_write32(1, lb(S1
, S0
, 0));
734 gs
.dr_write32(1, lh(S1
, S0
, 0));
737 gs
.dr_write32(1, lw(S1
, S0
, 0));
740 gs
.dr_write32(1, ld(S1
, S0
, 0));
743 gs
.dr_write_store(2, S1
, SLOT_DATA1
);
745 gs
.dr_write(SLOT_DATA0
, paddr
);
751 if (gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1)) {
752 // Note that OpenOCD doesn't report this error to gdb by default. They
753 // think it can mess up stack tracing. So far I haven't seen any
755 gs
.send_packet("E99");
759 reg_t value
= gs
.dr_read(SLOT_DATA1
);
760 for (unsigned int i
= 0; i
< access_size
; i
++) {
762 *(data
++) = value
& 0xff;
763 D(fprintf(stderr
, "%02x", (unsigned int) (value
& 0xff)));
765 buf
[index
++] = value
& 0xff;
770 D(fprintf(stderr
, "\n"));
772 length
-= access_size
;
773 paddr
+= access_size
;
779 for (unsigned int i
= 0; i
< index
; i
++) {
780 sprintf(buffer
, "%02x", (unsigned int) buf
[i
]);
787 gs
.dr_write(SLOT_DATA0
, paddr
);
798 unsigned int access_size
;
803 class memory_write_op_t
: public operation_t
806 memory_write_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
807 const unsigned char *data
) :
808 operation_t(gdbserver
), vaddr(vaddr
), offset(0), length(length
), data(data
) {};
810 ~memory_write_op_t() {
814 bool perform_step(unsigned int step
)
816 reg_t paddr
= gs
.translate(vaddr
);
818 unsigned int data_offset
;
821 data_offset
= slot_offset32
[SLOT_DATA1
];
824 data_offset
= slot_offset64
[SLOT_DATA1
];
827 data_offset
= slot_offset128
[SLOT_DATA1
];
834 access_size
= gs
.find_access_size(paddr
, length
);
836 D(fprintf(stderr
, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr
, paddr
,
838 for (unsigned int i
= 0; i
< length
; i
++) {
839 D(fprintf(stderr
, "%02x", data
[i
]));
841 D(fprintf(stderr
, "\n"));
843 // address goes in S0
844 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
845 switch (access_size
) {
847 gs
.dr_write32(1, lb(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
848 gs
.dr_write32(2, sb(S1
, S0
, 0));
849 gs
.dr_write32(data_offset
, data
[0]);
852 gs
.dr_write32(1, lh(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
853 gs
.dr_write32(2, sh(S1
, S0
, 0));
854 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8));
857 gs
.dr_write32(1, lw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
858 gs
.dr_write32(2, sw(S1
, S0
, 0));
859 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8) |
860 (data
[2] << 16) | (data
[3] << 24));
863 gs
.dr_write32(1, ld(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
864 gs
.dr_write32(2, sd(S1
, S0
, 0));
865 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8) |
866 (data
[2] << 16) | (data
[3] << 24));
867 gs
.dr_write32(data_offset
+1, data
[4] | (data
[5] << 8) |
868 (data
[6] << 16) | (data
[7] << 24));
871 fprintf(stderr
, "gdbserver error: write %d bytes to 0x%016" PRIx64
872 " -> 0x%016" PRIx64
"; access_size=%d\n",
873 length
, vaddr
, paddr
, access_size
);
874 gs
.send_packet("E12");
878 gs
.dr_write(SLOT_DATA0
, paddr
);
884 if (gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1)) {
885 fprintf(stderr
, "Exception happened while writing to 0x%016" PRIx64
886 " -> 0x%016" PRIx64
"\n", vaddr
, paddr
);
889 offset
+= access_size
;
890 if (offset
>= length
) {
891 gs
.send_packet("OK");
894 const unsigned char *d
= data
+ offset
;
895 switch (access_size
) {
897 gs
.dr_write32(data_offset
, d
[0]);
900 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8));
903 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8) |
904 (d
[2] << 16) | (d
[3] << 24));
907 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8) |
908 (d
[2] << 16) | (d
[3] << 24));
909 gs
.dr_write32(data_offset
+1, d
[4] | (d
[5] << 8) |
910 (d
[6] << 16) | (d
[7] << 24));
913 gs
.send_packet("E13");
916 gs
.dr_write(SLOT_DATA0
, paddr
+ offset
);
926 unsigned int access_size
;
927 const unsigned char *data
;
930 class collect_translation_info_op_t
: public operation_t
933 // Read sufficient information from the target into gdbserver structures so
934 // that it's possible to translate vaddr, vaddr+length, and all addresses
935 // in between to physical addresses.
936 collect_translation_info_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, size_t length
) :
937 operation_t(gdbserver
), state(STATE_START
), vaddr(vaddr
), length(length
) {};
939 bool perform_step(unsigned int step
)
941 unsigned int vm
= gs
.virtual_memory();
946 // Nothing to be done.
968 sprintf(buf
, "VM mode %d is not supported by gdbserver.cc.", vm
);
970 return true; // die doesn't return, but gcc doesn't know that.
975 // Perform any reads from the just-completed action.
979 case STATE_READ_SPTBR
:
980 gs
.sptbr
= gs
.dr_read(SLOT_DATA0
);
981 gs
.sptbr_valid
= true;
985 gs
.pte_cache
[pte_addr
] = gs
.dr_read32(4);
987 gs
.pte_cache
[pte_addr
] = ((uint64_t) gs
.dr_read32(5) << 32) |
990 D(fprintf(stderr
, "pte_cache[0x%lx] = 0x%lx\n", pte_addr
, gs
.pte_cache
[pte_addr
]));
994 // Set up the next action.
995 // We only get here for VM_SV32/39/38.
997 if (!gs
.sptbr_valid
) {
998 state
= STATE_READ_SPTBR
;
999 gs
.dr_write32(0, csrr(S0
, CSR_SPTBR
));
1000 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1001 gs
.dr_write_jump(2);
1002 gs
.set_interrupt(0);
1006 reg_t base
= gs
.sptbr
<< PGSHIFT
;
1007 int ptshift
= (levels
- 1) * ptidxbits
;
1008 for (unsigned int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
1009 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
1011 pte_addr
= base
+ idx
* ptesize
;
1012 auto it
= gs
.pte_cache
.find(pte_addr
);
1013 if (it
== gs
.pte_cache
.end()) {
1014 state
= STATE_READ_PTE
;
1016 gs
.dr_write32(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1017 gs
.dr_write32(1, lw(S1
, S0
, 0));
1018 gs
.dr_write32(2, sw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1020 assert(gs
.xlen
>= 64);
1021 gs
.dr_write32(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1022 gs
.dr_write32(1, ld(S1
, S0
, 0));
1023 gs
.dr_write32(2, sd(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1025 gs
.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*3))));
1026 gs
.dr_write32(4, pte_addr
);
1027 gs
.dr_write32(5, pte_addr
>> 32);
1028 gs
.set_interrupt(0);
1032 reg_t pte
= gs
.pte_cache
[pte_addr
];
1033 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
1035 if (PTE_TABLE(pte
)) { // next level of page table
1036 base
= ppn
<< PGSHIFT
;
1038 // We've collected all the data required for the translation.
1043 "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%016" PRIx64
"\n",
1056 unsigned int levels
;
1057 unsigned int ptidxbits
;
1058 unsigned int ptesize
;
1062 class hardware_breakpoint_insert_op_t
: public operation_t
1065 hardware_breakpoint_insert_op_t(gdbserver_t
& gdbserver
,
1066 hardware_breakpoint_t bp
) :
1067 operation_t(gdbserver
), state(STATE_START
), bp(bp
) {};
1069 void write_new_index_program()
1071 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1072 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1073 gs
.dr_write32(2, csrr(S0
, CSR_TSELECT
));
1074 gs
.dr_write_store(3, S0
, SLOT_DATA1
);
1075 gs
.dr_write_jump(4);
1076 gs
.dr_write(SLOT_DATA1
, bp
.index
);
1079 bool perform_step(unsigned int step
)
1084 write_new_index_program();
1085 state
= STATE_CHECK_INDEX
;
1088 case STATE_CHECK_INDEX
:
1089 if (gs
.dr_read(SLOT_DATA1
) != bp
.index
) {
1090 // We've exhausted breakpoints without finding an appropriate one.
1091 gs
.send_packet("E58");
1095 gs
.dr_write32(0, csrr(S0
, CSR_TDATA1
));
1096 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1097 gs
.dr_write_jump(2);
1098 state
= STATE_CHECK_MCONTROL
;
1101 case STATE_CHECK_MCONTROL
:
1103 reg_t mcontrol
= gs
.dr_read(SLOT_DATA0
);
1104 unsigned int type
= mcontrol
>> (gs
.xlen
- 4);
1106 // We've exhausted breakpoints without finding an appropriate one.
1107 gs
.send_packet("E58");
1112 !get_field(mcontrol
, MCONTROL_EXECUTE
) &&
1113 !get_field(mcontrol
, MCONTROL_LOAD
) &&
1114 !get_field(mcontrol
, MCONTROL_STORE
)) {
1115 // Found an unused trigger.
1116 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1117 gs
.dr_write32(1, csrw(S0
, CSR_TDATA1
));
1118 gs
.dr_write_jump(2);
1119 mcontrol
= set_field(0, MCONTROL_ACTION
, MCONTROL_ACTION_DEBUG_MODE
);
1120 mcontrol
= set_field(mcontrol
, MCONTROL_DMODE(gs
.xlen
), 1);
1121 mcontrol
= set_field(mcontrol
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
1122 mcontrol
= set_field(mcontrol
, MCONTROL_M
, 1);
1123 mcontrol
= set_field(mcontrol
, MCONTROL_H
, 1);
1124 mcontrol
= set_field(mcontrol
, MCONTROL_S
, 1);
1125 mcontrol
= set_field(mcontrol
, MCONTROL_U
, 1);
1126 mcontrol
= set_field(mcontrol
, MCONTROL_EXECUTE
, bp
.execute
);
1127 mcontrol
= set_field(mcontrol
, MCONTROL_LOAD
, bp
.load
);
1128 mcontrol
= set_field(mcontrol
, MCONTROL_STORE
, bp
.store
);
1129 // For store triggers it's nicer to fire just before the
1130 // instruction than just after. However, gdb doesn't clear the
1131 // breakpoints and step before resuming from a store trigger.
1132 // That means that without extra code, you'll keep hitting the
1133 // same watchpoint over and over again. That's not useful at all.
1134 // Instead of fixing this the right way, just set timing=1 for
1136 if (bp
.load
|| bp
.store
)
1137 mcontrol
= set_field(mcontrol
, MCONTROL_TIMING
, 1);
1139 gs
.dr_write(SLOT_DATA1
, mcontrol
);
1140 state
= STATE_WRITE_ADDRESS
;
1143 write_new_index_program();
1144 state
= STATE_CHECK_INDEX
;
1149 case STATE_WRITE_ADDRESS
:
1151 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1152 gs
.dr_write32(1, csrw(S0
, CSR_TDATA2
));
1153 gs
.dr_write_jump(2);
1154 gs
.dr_write(SLOT_DATA1
, bp
.vaddr
);
1155 gs
.set_interrupt(0);
1156 gs
.send_packet("OK");
1158 gs
.hardware_breakpoints
.insert(bp
);
1164 gs
.set_interrupt(0);
1172 STATE_CHECK_MCONTROL
,
1175 hardware_breakpoint_t bp
;
1178 class maybe_save_tselect_op_t
: public operation_t
1181 maybe_save_tselect_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1182 bool perform_step(unsigned int step
) {
1183 if (gs
.tselect_valid
)
1188 gs
.dr_write32(0, csrr(S0
, CSR_TDATA1
));
1189 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1190 gs
.dr_write_jump(2);
1191 gs
.set_interrupt(0);
1194 gs
.tselect
= gs
.dr_read(SLOT_DATA0
);
1195 gs
.tselect_valid
= true;
1202 class maybe_restore_tselect_op_t
: public operation_t
1205 maybe_restore_tselect_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1206 bool perform_step(unsigned int step
) {
1207 if (gs
.tselect_valid
) {
1208 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1209 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1210 gs
.dr_write_jump(2);
1211 gs
.dr_write(SLOT_DATA1
, gs
.tselect
);
1217 class hardware_breakpoint_remove_op_t
: public operation_t
1220 hardware_breakpoint_remove_op_t(gdbserver_t
& gdbserver
,
1221 hardware_breakpoint_t bp
) :
1222 operation_t(gdbserver
), bp(bp
) {};
1224 bool perform_step(unsigned int step
) {
1225 gs
.dr_write32(0, addi(S0
, ZERO
, bp
.index
));
1226 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1227 gs
.dr_write32(2, csrw(ZERO
, CSR_TDATA1
));
1228 gs
.dr_write_jump(3);
1229 gs
.set_interrupt(0);
1234 hardware_breakpoint_t bp
;
1237 ////////////////////////////// gdbserver itself
1239 gdbserver_t::gdbserver_t(uint16_t port
, sim_t
*sim
) :
1243 recv_buf(64 * 1024), send_buf(64 * 1024)
1245 socket_fd
= socket(AF_INET
, SOCK_STREAM
, 0);
1246 if (socket_fd
== -1) {
1247 fprintf(stderr
, "failed to make socket: %s (%d)\n", strerror(errno
), errno
);
1251 fcntl(socket_fd
, F_SETFL
, O_NONBLOCK
);
1253 if (setsockopt(socket_fd
, SOL_SOCKET
, SO_REUSEADDR
, &reuseaddr
,
1254 sizeof(int)) == -1) {
1255 fprintf(stderr
, "failed setsockopt: %s (%d)\n", strerror(errno
), errno
);
1259 struct sockaddr_in addr
;
1260 memset(&addr
, 0, sizeof(addr
));
1261 addr
.sin_family
= AF_INET
;
1262 addr
.sin_addr
.s_addr
= INADDR_ANY
;
1263 addr
.sin_port
= htons(port
);
1265 if (bind(socket_fd
, (struct sockaddr
*) &addr
, sizeof(addr
)) == -1) {
1266 fprintf(stderr
, "failed to bind socket: %s (%d)\n", strerror(errno
), errno
);
1270 if (listen(socket_fd
, 1) == -1) {
1271 fprintf(stderr
, "failed to listen on socket: %s (%d)\n", strerror(errno
), errno
);
1276 unsigned int gdbserver_t::find_access_size(reg_t address
, int length
)
1278 reg_t composite
= address
| length
;
1279 if ((composite
& 0x7) == 0 && xlen
>= 64)
1281 if ((composite
& 0x3) == 0)
1286 reg_t
gdbserver_t::translate(reg_t vaddr
)
1288 unsigned int vm
= virtual_memory();
1289 unsigned int levels
, ptidxbits
, ptesize
;
1314 sprintf(buf
, "VM mode %d is not supported by gdbserver.cc.", vm
);
1316 return true; // die doesn't return, but gcc doesn't know that.
1320 // Handle page tables here. There's a bunch of duplicated code with
1321 // collect_translation_info_op_t. :-(
1322 reg_t base
= sptbr
<< PGSHIFT
;
1323 int ptshift
= (levels
- 1) * ptidxbits
;
1324 for (unsigned int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
1325 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
1327 reg_t pte_addr
= base
+ idx
* ptesize
;
1328 auto it
= pte_cache
.find(pte_addr
);
1329 if (it
== pte_cache
.end()) {
1330 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1331 " without first collecting the relevant PTEs.\n", vaddr
);
1332 die("gdbserver_t::translate()");
1335 reg_t pte
= pte_cache
[pte_addr
];
1336 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
1338 if (PTE_TABLE(pte
)) { // next level of page table
1339 base
= ppn
<< PGSHIFT
;
1341 // We've collected all the data required for the translation.
1342 reg_t vpn
= vaddr
>> PGSHIFT
;
1343 reg_t paddr
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
1344 paddr
+= vaddr
& (PGSIZE
-1);
1345 D(fprintf(stderr
, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr
, paddr
));
1350 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1351 " but the relevant PTEs are invalid.\n", vaddr
);
1352 // TODO: Is it better to throw an exception here?
1356 unsigned int gdbserver_t::privilege_mode()
1358 unsigned int mode
= get_field(dcsr
, DCSR_PRV
);
1359 if (get_field(mstatus
, MSTATUS_MPRV
))
1360 mode
= get_field(mstatus
, MSTATUS_MPP
);
1364 unsigned int gdbserver_t::virtual_memory()
1366 unsigned int mode
= privilege_mode();
1369 return get_field(mstatus
, MSTATUS_VM
);
1372 void gdbserver_t::dr_write32(unsigned int index
, uint32_t value
)
1374 sim
->debug_module
.ram_write32(index
, value
);
1377 void gdbserver_t::dr_write64(unsigned int index
, uint64_t value
)
1379 dr_write32(index
, value
);
1380 dr_write32(index
+1, value
>> 32);
1383 void gdbserver_t::dr_write(enum slot slot
, uint64_t value
)
1387 dr_write32(slot_offset32
[slot
], value
);
1390 dr_write64(slot_offset64
[slot
], value
);
1398 void gdbserver_t::dr_write_jump(unsigned int index
)
1400 dr_write32(index
, jal(0,
1401 (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*index
))));
1404 void gdbserver_t::dr_write_store(unsigned int index
, unsigned int reg
, enum slot slot
)
1406 assert(slot
!= SLOT_INST0
|| index
> 2);
1407 assert(slot
!= SLOT_DATA0
|| index
< 4 || index
> 6);
1408 assert(slot
!= SLOT_DATA1
|| index
< 5 || index
> 10);
1409 assert(slot
!= SLOT_DATA_LAST
|| index
< 6 || index
> 14);
1412 return dr_write32(index
,
1413 sw(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset32
[slot
]));
1415 return dr_write32(index
,
1416 sd(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset64
[slot
]));
1418 return dr_write32(index
,
1419 sq(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset128
[slot
]));
1421 fprintf(stderr
, "xlen is %d!\n", xlen
);
1426 void gdbserver_t::dr_write_load(unsigned int index
, unsigned int reg
, enum slot slot
)
1430 return dr_write32(index
,
1431 lw(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset32
[slot
]));
1433 return dr_write32(index
,
1434 ld(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset64
[slot
]));
1436 return dr_write32(index
,
1437 lq(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset128
[slot
]));
1439 fprintf(stderr
, "xlen is %d!\n", xlen
);
1444 uint32_t gdbserver_t::dr_read32(unsigned int index
)
1446 uint32_t value
= sim
->debug_module
.ram_read32(index
);
1447 D(fprintf(stderr
, "read32(%d) -> 0x%x\n", index
, value
));
1451 uint64_t gdbserver_t::dr_read64(unsigned int index
)
1453 return ((uint64_t) dr_read32(index
+1) << 32) | dr_read32(index
);
1456 uint64_t gdbserver_t::dr_read(enum slot slot
)
1460 return dr_read32(slot_offset32
[slot
]);
1462 return dr_read64(slot_offset64
[slot
]);
1470 void gdbserver_t::add_operation(operation_t
* operation
)
1472 operation_queue
.push(operation
);
1475 void gdbserver_t::accept()
1477 client_fd
= ::accept(socket_fd
, NULL
, NULL
);
1478 if (client_fd
== -1) {
1479 if (errno
== EAGAIN
) {
1480 // No client waiting to connect right now.
1482 fprintf(stderr
, "failed to accept on socket: %s (%d)\n", strerror(errno
),
1487 fcntl(client_fd
, F_SETFL
, O_NONBLOCK
);
1490 extended_mode
= false;
1492 // gdb wants the core to be halted when it attaches.
1493 add_operation(new halt_op_t(*this));
1497 void gdbserver_t::read()
1499 // Reading from a non-blocking socket still blocks if there is no data
1502 size_t count
= recv_buf
.contiguous_empty_size();
1504 ssize_t bytes
= ::read(client_fd
, recv_buf
.contiguous_empty(), count
);
1506 if (errno
== EAGAIN
) {
1507 // We'll try again the next call.
1509 fprintf(stderr
, "failed to read on socket: %s (%d)\n", strerror(errno
), errno
);
1512 } else if (bytes
== 0) {
1513 // The remote disconnected.
1515 processor_t
*p
= sim
->get_core(0);
1516 // TODO p->set_halted(false, HR_NONE);
1520 recv_buf
.data_added(bytes
);
1524 void gdbserver_t::write()
1526 if (send_buf
.empty())
1529 while (!send_buf
.empty()) {
1530 unsigned int count
= send_buf
.contiguous_data_size();
1532 ssize_t bytes
= ::write(client_fd
, send_buf
.contiguous_data(), count
);
1534 fprintf(stderr
, "failed to write to socket: %s (%d)\n", strerror(errno
), errno
);
1536 } else if (bytes
== 0) {
1537 // Client can't take any more data right now.
1540 D(fprintf(stderr
, "wrote %ld bytes: ", bytes
));
1541 for (unsigned int i
= 0; i
< bytes
; i
++) {
1542 D(fprintf(stderr
, "%c", send_buf
[i
]));
1544 D(fprintf(stderr
, "\n"));
1545 send_buf
.consume(bytes
);
1550 void print_packet(const std::vector
<uint8_t> &packet
)
1552 for (uint8_t c
: packet
) {
1553 if (c
>= ' ' and c
<= '~')
1554 fprintf(stderr
, "%c", c
);
1556 fprintf(stderr
, "\\x%02x", c
);
1558 fprintf(stderr
, "\n");
1561 uint8_t compute_checksum(const std::vector
<uint8_t> &packet
)
1563 uint8_t checksum
= 0;
1564 for (auto i
= packet
.begin() + 1; i
!= packet
.end() - 3; i
++ ) {
1570 uint8_t character_hex_value(uint8_t character
)
1572 if (character
>= '0' && character
<= '9')
1573 return character
- '0';
1574 if (character
>= 'a' && character
<= 'f')
1575 return 10 + character
- 'a';
1576 if (character
>= 'A' && character
<= 'F')
1577 return 10 + character
- 'A';
1581 uint8_t extract_checksum(const std::vector
<uint8_t> &packet
)
1583 return character_hex_value(*(packet
.end() - 1)) +
1584 16 * character_hex_value(*(packet
.end() - 2));
1587 void gdbserver_t::process_requests()
1589 // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1591 while (!recv_buf
.empty()) {
1592 std::vector
<uint8_t> packet
;
1593 for (unsigned int i
= 0; i
< recv_buf
.size(); i
++) {
1594 uint8_t b
= recv_buf
[i
];
1596 if (packet
.empty() && expect_ack
&& b
== '+') {
1597 recv_buf
.consume(1);
1601 if (packet
.empty() && b
== 3) {
1602 D(fprintf(stderr
, "Received interrupt\n"));
1603 recv_buf
.consume(1);
1609 // Start of new packet.
1610 if (!packet
.empty()) {
1611 fprintf(stderr
, "Received malformed %ld-byte packet from debug client: ",
1613 print_packet(packet
);
1614 recv_buf
.consume(i
);
1619 packet
.push_back(b
);
1621 // Packets consist of $<packet-data>#<checksum>
1622 // where <checksum> is
1623 if (packet
.size() >= 4 &&
1624 packet
[packet
.size()-3] == '#') {
1625 handle_packet(packet
);
1626 recv_buf
.consume(i
+1);
1630 // There's a partial packet in the buffer. Wait until we get more data to
1632 if (packet
.size()) {
1638 void gdbserver_t::handle_halt_reason(const std::vector
<uint8_t> &packet
)
1643 void gdbserver_t::handle_general_registers_read(const std::vector
<uint8_t> &packet
)
1645 add_operation(new general_registers_read_op_t(*this));
1648 void gdbserver_t::set_interrupt(uint32_t hartid
) {
1649 sim
->debug_module
.set_interrupt(hartid
);
1652 // First byte is the most-significant one.
1653 // Eg. "08675309" becomes 0x08675309.
1654 uint64_t consume_hex_number(std::vector
<uint8_t>::const_iterator
&iter
,
1655 std::vector
<uint8_t>::const_iterator end
)
1659 while (iter
!= end
) {
1661 uint64_t c_value
= character_hex_value(c
);
1671 // First byte is the least-significant one.
1672 // Eg. "08675309" becomes 0x09536708
1673 uint64_t consume_hex_number_le(std::vector
<uint8_t>::const_iterator
&iter
,
1674 std::vector
<uint8_t>::const_iterator end
)
1677 unsigned int shift
= 4;
1679 while (iter
!= end
) {
1681 uint64_t c_value
= character_hex_value(c
);
1685 value
|= c_value
<< shift
;
1686 if ((shift
% 8) == 0)
1694 void consume_string(std::string
&str
, std::vector
<uint8_t>::const_iterator
&iter
,
1695 std::vector
<uint8_t>::const_iterator end
, uint8_t separator
)
1697 while (iter
!= end
&& *iter
!= separator
) {
1698 str
.append(1, (char) *iter
);
1703 void gdbserver_t::handle_register_read(const std::vector
<uint8_t> &packet
)
1707 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1708 unsigned int n
= consume_hex_number(iter
, packet
.end());
1710 return send_packet("E01");
1712 add_operation(new register_read_op_t(*this, n
));
1715 void gdbserver_t::handle_register_write(const std::vector
<uint8_t> &packet
)
1719 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1720 unsigned int n
= consume_hex_number(iter
, packet
.end());
1722 return send_packet("E05");
1725 reg_t value
= consume_hex_number_le(iter
, packet
.end());
1727 return send_packet("E06");
1729 processor_t
*p
= sim
->get_core(0);
1731 add_operation(new register_write_op_t(*this, n
, value
));
1733 return send_packet("OK");
1736 void gdbserver_t::handle_memory_read(const std::vector
<uint8_t> &packet
)
1739 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1740 reg_t address
= consume_hex_number(iter
, packet
.end());
1742 return send_packet("E10");
1744 reg_t length
= consume_hex_number(iter
, packet
.end());
1746 return send_packet("E11");
1748 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1749 add_operation(new memory_read_op_t(*this, address
, length
));
1752 void gdbserver_t::handle_memory_binary_write(const std::vector
<uint8_t> &packet
)
1754 // X addr,length:XX...
1755 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1756 reg_t address
= consume_hex_number(iter
, packet
.end());
1758 return send_packet("E20");
1760 reg_t length
= consume_hex_number(iter
, packet
.end());
1762 return send_packet("E21");
1766 return send_packet("OK");
1769 unsigned char *data
= new unsigned char[length
];
1770 for (unsigned int i
= 0; i
< length
; i
++) {
1771 if (iter
== packet
.end()) {
1772 return send_packet("E22");
1777 // The binary data representation uses 7d (ascii ‘}’) as an escape
1778 // character. Any escaped byte is transmitted as the escape character
1779 // followed by the original character XORed with 0x20. For example, the
1780 // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1781 // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1783 if (iter
== packet
.end()) {
1784 return send_packet("E23");
1792 return send_packet("E4b"); // EOVERFLOW
1794 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1795 add_operation(new memory_write_op_t(*this, address
, length
, data
));
1798 void gdbserver_t::handle_continue(const std::vector
<uint8_t> &packet
)
1801 processor_t
*p
= sim
->get_core(0);
1802 if (packet
[2] != '#') {
1803 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1804 dpc
= consume_hex_number(iter
, packet
.end());
1806 return send_packet("E30");
1809 add_operation(new maybe_restore_tselect_op_t(*this));
1810 add_operation(new continue_op_t(*this, false));
1813 void gdbserver_t::handle_step(const std::vector
<uint8_t> &packet
)
1816 if (packet
[2] != '#') {
1817 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1819 //p->state.pc = consume_hex_number(iter, packet.end());
1821 return send_packet("E40");
1824 add_operation(new maybe_restore_tselect_op_t(*this));
1825 add_operation(new continue_op_t(*this, true));
1828 void gdbserver_t::handle_kill(const std::vector
<uint8_t> &packet
)
1831 // The exact effect of this packet is not specified.
1832 // Looks like OpenOCD disconnects?
1836 void gdbserver_t::handle_extended(const std::vector
<uint8_t> &packet
)
1838 // Enable extended mode. In extended mode, the remote server is made
1839 // persistent. The ‘R’ packet is used to restart the program being debugged.
1841 extended_mode
= true;
1844 void gdbserver_t::software_breakpoint_insert(reg_t vaddr
, unsigned int size
)
1846 fence_i_required
= true;
1847 add_operation(new collect_translation_info_op_t(*this, vaddr
, size
));
1848 unsigned char* inst
= new unsigned char[4];
1850 inst
[0] = C_EBREAK
& 0xff;
1851 inst
[1] = (C_EBREAK
>> 8) & 0xff;
1853 inst
[0] = EBREAK
& 0xff;
1854 inst
[1] = (EBREAK
>> 8) & 0xff;
1855 inst
[2] = (EBREAK
>> 16) & 0xff;
1856 inst
[3] = (EBREAK
>> 24) & 0xff;
1859 software_breakpoint_t bp
= {
1863 software_breakpoints
[vaddr
] = bp
;
1864 add_operation(new memory_read_op_t(*this, bp
.vaddr
, bp
.size
,
1865 software_breakpoints
[bp
.vaddr
].instruction
));
1866 add_operation(new memory_write_op_t(*this, bp
.vaddr
, bp
.size
, inst
));
1869 void gdbserver_t::software_breakpoint_remove(reg_t vaddr
, unsigned int size
)
1871 fence_i_required
= true;
1872 add_operation(new collect_translation_info_op_t(*this, vaddr
, size
));
1874 software_breakpoint_t found_bp
= software_breakpoints
[vaddr
];
1875 unsigned char* instruction
= new unsigned char[4];
1876 memcpy(instruction
, found_bp
.instruction
, 4);
1877 add_operation(new memory_write_op_t(*this, found_bp
.vaddr
,
1878 found_bp
.size
, instruction
));
1879 software_breakpoints
.erase(vaddr
);
1882 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t
&bp
)
1884 add_operation(new maybe_save_tselect_op_t(*this));
1885 add_operation(new hardware_breakpoint_insert_op_t(*this, bp
));
1888 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t
&bp
)
1890 add_operation(new maybe_save_tselect_op_t(*this));
1891 hardware_breakpoint_t found
= *hardware_breakpoints
.find(bp
);
1892 add_operation(new hardware_breakpoint_remove_op_t(*this, found
));
1895 void gdbserver_t::handle_breakpoint(const std::vector
<uint8_t> &packet
)
1897 // insert: Z type,addr,length
1898 // remove: z type,addr,length
1900 // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1901 // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1902 // length is in bytes. For a software breakpoint, length specifies the size
1903 // of the instruction to be patched. For hardware breakpoints and watchpoints
1904 // length specifies the memory region to be monitored. To avoid potential
1905 // problems with duplicate packets, the operations should be implemented in
1906 // an idempotent way.
1908 bool insert
= (packet
[1] == 'Z');
1909 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1910 gdb_breakpoint_type_t type
= static_cast<gdb_breakpoint_type_t
>(
1911 consume_hex_number(iter
, packet
.end()));
1913 return send_packet("E50");
1915 reg_t address
= consume_hex_number(iter
, packet
.end());
1917 return send_packet("E51");
1919 unsigned int size
= consume_hex_number(iter
, packet
.end());
1920 // There may be more options after a ; here, but we don't support that.
1922 return send_packet("E52");
1926 if (size
!= 2 && size
!= 4) {
1927 return send_packet("E53");
1930 software_breakpoint_insert(address
, size
);
1932 software_breakpoint_remove(address
, size
);
1941 hardware_breakpoint_t bp
= {
1945 bp
.load
= (type
== GB_READ
|| type
== GB_ACCESS
);
1946 bp
.store
= (type
== GB_WRITE
|| type
== GB_ACCESS
);
1947 bp
.execute
= (type
== GB_HARDWARE
|| type
== GB_ACCESS
);
1949 hardware_breakpoint_insert(bp
);
1950 // Insert might fail if there's no space, so the insert operation will
1951 // send its own OK (or not).
1954 hardware_breakpoint_remove(bp
);
1960 return send_packet("E56");
1963 return send_packet("OK");
1966 void gdbserver_t::handle_query(const std::vector
<uint8_t> &packet
)
1969 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1971 consume_string(name
, iter
, packet
.end(), ':');
1972 if (iter
!= packet
.end())
1974 if (name
== "Supported") {
1976 while (iter
!= packet
.end()) {
1977 std::string feature
;
1978 consume_string(feature
, iter
, packet
.end(), ';');
1979 if (iter
!= packet
.end())
1981 if (feature
== "swbreak+") {
1985 send("PacketSize=131072;");
1986 return end_packet();
1989 D(fprintf(stderr
, "Unsupported query %s\n", name
.c_str()));
1990 return send_packet("");
1993 void gdbserver_t::handle_packet(const std::vector
<uint8_t> &packet
)
1995 if (compute_checksum(packet
) != extract_checksum(packet
)) {
1996 fprintf(stderr
, "Received %ld-byte packet with invalid checksum\n", packet
.size());
1997 fprintf(stderr
, "Computed checksum: %x\n", compute_checksum(packet
));
1998 print_packet(packet
);
2003 D(fprintf(stderr
, "Received %ld-byte packet from debug client: ", packet
.size()));
2004 D(print_packet(packet
));
2007 switch (packet
[1]) {
2009 return handle_extended(packet
);
2011 return handle_halt_reason(packet
);
2013 return handle_general_registers_read(packet
);
2015 // return handle_kill(packet);
2017 return handle_memory_read(packet
);
2019 // return handle_memory_write(packet);
2021 return handle_memory_binary_write(packet
);
2023 return handle_register_read(packet
);
2025 return handle_register_write(packet
);
2027 return handle_continue(packet
);
2029 return handle_step(packet
);
2032 return handle_breakpoint(packet
);
2035 return handle_query(packet
);
2039 D(fprintf(stderr
, "** Unsupported packet: "));
2040 D(print_packet(packet
));
2044 void gdbserver_t::handle_interrupt()
2046 processor_t
*p
= sim
->get_core(0);
2047 add_operation(new halt_op_t(*this, true));
2050 void gdbserver_t::handle()
2052 if (client_fd
> 0) {
2053 processor_t
*p
= sim
->get_core(0);
2055 bool interrupt
= sim
->debug_module
.get_interrupt(0);
2057 if (!interrupt
&& !operation_queue
.empty()) {
2058 operation_t
*operation
= operation_queue
.front();
2059 if (operation
->step()) {
2060 operation_queue
.pop();
2065 bool halt_notification
= sim
->debug_module
.get_halt_notification(0);
2066 if (halt_notification
) {
2067 sim
->debug_module
.clear_halt_notification(0);
2068 add_operation(new halt_op_t(*this, true));
2078 if (operation_queue
.empty()) {
2079 this->process_requests();
2083 void gdbserver_t::send(const char* msg
)
2085 unsigned int length
= strlen(msg
);
2086 for (const char *c
= msg
; *c
; c
++)
2087 running_checksum
+= *c
;
2088 send_buf
.append((const uint8_t *) msg
, length
);
2091 void gdbserver_t::send(uint64_t value
)
2094 for (unsigned int i
= 0; i
< 8; i
++) {
2095 sprintf(buffer
, "%02x", (int) (value
& 0xff));
2101 void gdbserver_t::send(uint32_t value
)
2104 for (unsigned int i
= 0; i
< 4; i
++) {
2105 sprintf(buffer
, "%02x", (int) (value
& 0xff));
2111 void gdbserver_t::send(uint8_t value
)
2114 sprintf(buffer
, "%02x", (int) value
);
2118 void gdbserver_t::send_packet(const char* data
)
2126 void gdbserver_t::start_packet()
2129 running_checksum
= 0;
2132 void gdbserver_t::end_packet(const char* data
)
2138 char checksum_string
[4];
2139 sprintf(checksum_string
, "#%02x", running_checksum
);
2140 send(checksum_string
);