6 #include <sys/socket.h>
17 #include "gdbserver.h"
20 #define C_EBREAK 0x9002
21 #define EBREAK 0x00100073
23 //////////////////////////////////////// Utility Functions
25 void die(const char* msg
)
27 fprintf(stderr
, "gdbserver code died: %s\n", msg
);
31 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
32 // its source tree. We must interpret the numbers the same here.
44 // Return access size to use when writing length bytes to address, so that
45 // every write will be aligned.
46 unsigned int find_access_size(reg_t address
, int length
)
48 reg_t composite
= address
| length
;
49 if ((composite
& 0x7) == 0)
51 if ((composite
& 0x3) == 0)
56 //////////////////////////////////////// Functions to generate RISC-V opcodes.
58 // TODO: Does this already exist somewhere?
60 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
61 // spec says it should be 2 and 3.
64 static uint32_t bits(uint32_t value
, unsigned int hi
, unsigned int lo
) {
65 return (value
>> lo
) & ((1 << (hi
+1-lo
)) - 1);
68 static uint32_t bit(uint32_t value
, unsigned int b
) {
69 return (value
>> b
) & 1;
72 static uint32_t jal(unsigned int rd
, uint32_t imm
) {
73 return (bit(imm
, 20) << 31) |
74 (bits(imm
, 10, 1) << 21) |
75 (bit(imm
, 11) << 20) |
76 (bits(imm
, 19, 12) << 12) |
81 static uint32_t csrsi(unsigned int csr
, uint16_t imm
) {
83 (bits(imm
, 4, 0) << 15) |
87 static uint32_t csrci(unsigned int csr
, uint16_t imm
) {
89 (bits(imm
, 4, 0) << 15) |
93 static uint32_t csrr(unsigned int rd
, unsigned int csr
) {
94 return (csr
<< 20) | (rd
<< 7) | MATCH_CSRRS
;
97 static uint32_t csrw(unsigned int source
, unsigned int csr
) {
98 return (csr
<< 20) | (source
<< 15) | MATCH_CSRRW
;
101 static uint32_t fence_i()
103 return MATCH_FENCE_I
;
106 static uint32_t sb(unsigned int src
, unsigned int base
, uint16_t offset
)
108 return (bits(offset
, 11, 5) << 25) |
111 (bits(offset
, 4, 0) << 7) |
115 static uint32_t sh(unsigned int src
, unsigned int base
, uint16_t offset
)
117 return (bits(offset
, 11, 5) << 25) |
120 (bits(offset
, 4, 0) << 7) |
124 static uint32_t sw(unsigned int src
, unsigned int base
, uint16_t offset
)
126 return (bits(offset
, 11, 5) << 25) |
129 (bits(offset
, 4, 0) << 7) |
133 static uint32_t sd(unsigned int src
, unsigned int base
, uint16_t offset
)
135 return (bits(offset
, 11, 5) << 25) |
136 (bits(src
, 4, 0) << 20) |
138 (bits(offset
, 4, 0) << 7) |
142 static uint32_t ld(unsigned int rd
, unsigned int base
, uint16_t offset
)
144 return (bits(offset
, 11, 0) << 20) |
146 (bits(rd
, 4, 0) << 7) |
150 static uint32_t lw(unsigned int rd
, unsigned int base
, uint16_t offset
)
152 return (bits(offset
, 11, 0) << 20) |
154 (bits(rd
, 4, 0) << 7) |
158 static uint32_t lh(unsigned int rd
, unsigned int base
, uint16_t offset
)
160 return (bits(offset
, 11, 0) << 20) |
162 (bits(rd
, 4, 0) << 7) |
166 static uint32_t lb(unsigned int rd
, unsigned int base
, uint16_t offset
)
168 return (bits(offset
, 11, 0) << 20) |
170 (bits(rd
, 4, 0) << 7) |
174 static uint32_t fsd(unsigned int src
, unsigned int base
, uint16_t offset
)
176 return (bits(offset
, 11, 5) << 25) |
177 (bits(src
, 4, 0) << 20) |
179 (bits(offset
, 4, 0) << 7) |
183 static uint32_t fld(unsigned int src
, unsigned int base
, uint16_t offset
)
185 return (bits(offset
, 11, 5) << 25) |
186 (bits(src
, 4, 0) << 20) |
188 (bits(offset
, 4, 0) << 7) |
192 static uint32_t addi(unsigned int dest
, unsigned int src
, uint16_t imm
)
194 return (bits(imm
, 11, 0) << 20) |
200 static uint32_t ori(unsigned int dest
, unsigned int src
, uint16_t imm
)
202 return (bits(imm
, 11, 0) << 20) |
208 static uint32_t nop()
210 return addi(0, 0, 0);
213 template <typename T
>
214 unsigned int circular_buffer_t
<T
>::size() const
219 return end
+ capacity
- start
;
222 template <typename T
>
223 void circular_buffer_t
<T
>::consume(unsigned int bytes
)
225 start
= (start
+ bytes
) % capacity
;
228 template <typename T
>
229 unsigned int circular_buffer_t
<T
>::contiguous_empty_size() const
233 return capacity
- end
- 1;
235 return capacity
- end
;
237 return start
- end
- 1;
240 template <typename T
>
241 unsigned int circular_buffer_t
<T
>::contiguous_data_size() const
246 return capacity
- start
;
249 template <typename T
>
250 void circular_buffer_t
<T
>::data_added(unsigned int bytes
)
253 assert(end
<= capacity
);
258 template <typename T
>
259 void circular_buffer_t
<T
>::reset()
265 template <typename T
>
266 void circular_buffer_t
<T
>::append(const T
*src
, unsigned int count
)
268 unsigned int copy
= std::min(count
, contiguous_empty_size());
269 memcpy(contiguous_empty(), src
, copy
* sizeof(T
));
273 assert(count
< contiguous_empty_size());
274 memcpy(contiguous_empty(), src
, count
* sizeof(T
));
279 ////////////////////////////// Debug Operations
281 class halt_op_t
: public operation_t
284 halt_op_t(gdbserver_t
& gdbserver
, bool send_status
=false) :
285 operation_t(gdbserver
), send_status(send_status
) {};
287 bool perform_step(unsigned int step
) {
290 // TODO: For now we just assume the target is 64-bit.
291 gs
.write_debug_ram(0, csrsi(CSR_DCSR
, DCSR_HALT
));
292 gs
.write_debug_ram(1, csrr(S0
, CSR_DPC
));
293 gs
.write_debug_ram(2, sd(S0
, 0, (uint16_t) DEBUG_RAM_START
));
294 gs
.write_debug_ram(3, csrr(S0
, CSR_MSTATUS
));
295 gs
.write_debug_ram(4, sd(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 8));
296 gs
.write_debug_ram(5, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*5))));
298 // We could read more registers here, but only on 64-bit targets. I'm
299 // trying to keep The patterns here usable for 32-bit ISAs as well.
303 gs
.dpc
= ((uint64_t) gs
.read_debug_ram(1) << 32) | gs
.read_debug_ram(0);
304 gs
.mstatus
= ((uint64_t) gs
.read_debug_ram(3) << 32) | gs
.read_debug_ram(2);
305 gs
.write_debug_ram(0, csrr(S0
, CSR_DCSR
));
306 gs
.write_debug_ram(1, sd(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
307 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*6))));
312 gs
.dcsr
= ((uint64_t) gs
.read_debug_ram(5) << 32) | gs
.read_debug_ram(4);
314 gs
.sptbr_valid
= false;
315 gs
.pte_cache
.clear();
318 switch (get_field(gs
.dcsr
, DCSR_CAUSE
)) {
319 case DCSR_CAUSE_NONE
:
320 fprintf(stderr
, "Internal error. Processor halted without reason.\n");
323 case DCSR_CAUSE_DEBUGINT
:
324 gs
.send_packet("S02"); // Pretend program received SIGINT.
327 case DCSR_CAUSE_HWBP
:
328 case DCSR_CAUSE_STEP
:
329 case DCSR_CAUSE_HALT
:
330 // There's no gdb code for this.
331 gs
.send_packet("T05");
333 case DCSR_CAUSE_SWBP
:
334 gs
.send_packet("T05swbreak:;");
348 class continue_op_t
: public operation_t
351 continue_op_t(gdbserver_t
& gdbserver
, bool single_step
) :
352 operation_t(gdbserver
), single_step(single_step
) {};
354 bool perform_step(unsigned int step
) {
357 gs
.write_debug_ram(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+16));
358 gs
.write_debug_ram(1, csrw(S0
, CSR_DPC
));
359 if (gs
.fence_i_required
) {
360 gs
.write_debug_ram(2, fence_i());
361 gs
.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*3))));
362 gs
.fence_i_required
= false;
364 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
366 gs
.write_debug_ram(4, gs
.dpc
);
367 gs
.write_debug_ram(5, gs
.dpc
>> 32);
372 gs
.write_debug_ram(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+16));
373 gs
.write_debug_ram(1, csrw(S0
, CSR_MSTATUS
));
374 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
375 gs
.write_debug_ram(4, gs
.mstatus
);
376 gs
.write_debug_ram(5, gs
.mstatus
>> 32);
381 gs
.write_debug_ram(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+16));
382 gs
.write_debug_ram(1, csrw(S0
, CSR_DCSR
));
383 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
385 reg_t dcsr
= set_field(gs
.dcsr
, DCSR_HALT
, 0);
386 dcsr
= set_field(dcsr
, DCSR_STEP
, single_step
);
387 // Software breakpoints should go here.
388 dcsr
= set_field(dcsr
, DCSR_EBREAKM
, 1);
389 dcsr
= set_field(dcsr
, DCSR_EBREAKH
, 1);
390 dcsr
= set_field(dcsr
, DCSR_EBREAKS
, 1);
391 dcsr
= set_field(dcsr
, DCSR_EBREAKU
, 1);
392 gs
.write_debug_ram(4, dcsr
);
404 class general_registers_read_op_t
: public operation_t
406 // Register order that gdb expects is:
407 // "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
408 // "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
409 // "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
410 // "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
412 // Each byte of register data is described by two hex digits. The bytes with
413 // the register are transmitted in target byte order. The size of each
414 // register and their position within the ‘g’ packet are determined by the
415 // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
416 // gdbarch_register_name.
419 general_registers_read_op_t(gdbserver_t
& gdbserver
) :
420 operation_t(gdbserver
) {};
422 bool perform_step(unsigned int step
)
427 // x0 is always zero.
430 gs
.write_debug_ram(0, sd(1, 0, (uint16_t) DEBUG_RAM_START
+ 16));
431 gs
.write_debug_ram(1, sd(2, 0, (uint16_t) DEBUG_RAM_START
+ 0));
432 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
437 gs
.send(((uint64_t) gs
.read_debug_ram(5) << 32) | gs
.read_debug_ram(4));
443 gs
.send(((uint64_t) gs
.read_debug_ram(1) << 32) | gs
.read_debug_ram(0));
445 unsigned int current_reg
= 2 * step
+ 1;
447 if (current_reg
== S1
) {
448 gs
.write_debug_ram(i
++, ld(S1
, 0, (uint16_t) DEBUG_RAM_END
- 8));
450 gs
.write_debug_ram(i
++, sd(current_reg
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
451 if (current_reg
+ 1 == S0
) {
452 gs
.write_debug_ram(i
++, csrr(S0
, CSR_DSCRATCH
));
454 gs
.write_debug_ram(i
++, sd(current_reg
+1, 0, (uint16_t) DEBUG_RAM_START
+ 0));
455 gs
.write_debug_ram(i
, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*i
))));
462 class register_read_op_t
: public operation_t
465 register_read_op_t(gdbserver_t
& gdbserver
, unsigned int reg
) :
466 operation_t(gdbserver
), reg(reg
) {};
468 bool perform_step(unsigned int step
)
472 if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
473 die("handle_register_read");
474 // send(p->state.XPR[reg - REG_XPR0]);
475 } else if (reg
== REG_PC
) {
480 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
481 // send(p->state.FPR[reg - REG_FPR0]);
482 gs
.write_debug_ram(0, fsd(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
483 gs
.write_debug_ram(1, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*1))));
484 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
485 gs
.write_debug_ram(0, csrr(S0
, reg
- REG_CSR0
));
486 gs
.write_debug_ram(1, sd(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
487 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
488 // If we hit an exception reading the CSR, we'll end up returning ~0 as
489 // the register's value, which is what we want. (Right?)
490 gs
.write_debug_ram(4, 0xffffffff);
491 gs
.write_debug_ram(5, 0xffffffff);
493 gs
.send_packet("E02");
501 gs
.send(((uint64_t) gs
.read_debug_ram(5) << 32) | gs
.read_debug_ram(4));
512 class register_write_op_t
: public operation_t
515 register_write_op_t(gdbserver_t
& gdbserver
, unsigned int reg
, reg_t value
) :
516 operation_t(gdbserver
), reg(reg
), value(value
) {};
518 bool perform_step(unsigned int step
)
520 gs
.write_debug_ram(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
521 gs
.write_debug_ram(4, value
);
522 gs
.write_debug_ram(5, value
>> 32);
524 gs
.write_debug_ram(1, csrw(S0
, CSR_DSCRATCH
));
525 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
526 } else if (reg
== S1
) {
527 gs
.write_debug_ram(1, sd(S0
, 0, (uint16_t) DEBUG_RAM_END
- 8));
528 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
529 } else if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
530 gs
.write_debug_ram(1, addi(reg
, S0
, 0));
531 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
532 } else if (reg
== REG_PC
) {
535 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
536 // send(p->state.FPR[reg - REG_FPR0]);
537 gs
.write_debug_ram(0, fld(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
538 gs
.write_debug_ram(1, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*1))));
539 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
540 gs
.write_debug_ram(1, csrw(S0
, reg
- REG_CSR0
));
541 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
542 if (reg
== REG_CSR0
+ CSR_SPTBR
) {
544 gs
.sptbr_valid
= true;
547 gs
.send_packet("E02");
551 gs
.send_packet("OK");
560 class memory_read_op_t
: public operation_t
563 // Read length bytes from vaddr, storing the result into data.
564 // If data is NULL, send the result straight to gdb.
565 memory_read_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
566 unsigned char *data
=NULL
) :
567 operation_t(gdbserver
), vaddr(vaddr
), length(length
), data(data
) {};
569 bool perform_step(unsigned int step
)
572 // address goes in S0
573 paddr
= gs
.translate(vaddr
);
574 access_size
= find_access_size(paddr
, length
);
576 gs
.write_debug_ram(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
577 switch (access_size
) {
579 gs
.write_debug_ram(1, lb(S1
, S0
, 0));
582 gs
.write_debug_ram(1, lh(S1
, S0
, 0));
585 gs
.write_debug_ram(1, lw(S1
, S0
, 0));
588 gs
.write_debug_ram(1, ld(S1
, S0
, 0));
591 gs
.write_debug_ram(2, sd(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 24));
592 gs
.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*3))));
593 gs
.write_debug_ram(4, paddr
);
594 gs
.write_debug_ram(5, paddr
>> 32);
604 reg_t value
= ((uint64_t) gs
.read_debug_ram(7) << 32) | gs
.read_debug_ram(6);
605 for (unsigned int i
= 0; i
< access_size
; i
++) {
607 *(data
++) = value
& 0xff;
608 fprintf(stderr
, "%02x", (unsigned int) (value
& 0xff));
610 sprintf(buffer
, "%02x", (unsigned int) (value
& 0xff));
616 fprintf(stderr
, "\n");
617 length
-= access_size
;
618 paddr
+= access_size
;
626 gs
.write_debug_ram(4, paddr
);
627 gs
.write_debug_ram(5, paddr
>> 32);
638 unsigned int access_size
;
641 class memory_write_op_t
: public operation_t
644 memory_write_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
645 const unsigned char *data
) :
646 operation_t(gdbserver
), vaddr(vaddr
), offset(0), length(length
), data(data
) {};
648 ~memory_write_op_t() {
652 bool perform_step(unsigned int step
)
654 reg_t paddr
= gs
.translate(vaddr
);
656 access_size
= find_access_size(paddr
, length
);
658 fprintf(stderr
, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr
, paddr
,
660 for (unsigned int i
= 0; i
< length
; i
++)
661 fprintf(stderr
, "%02x", data
[i
]);
662 fprintf(stderr
, "\n");
664 // address goes in S0
665 gs
.write_debug_ram(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
666 switch (access_size
) {
668 gs
.write_debug_ram(1, lb(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 24));
669 gs
.write_debug_ram(2, sb(S1
, S0
, 0));
670 gs
.write_debug_ram(6, data
[0]);
673 gs
.write_debug_ram(1, lh(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 24));
674 gs
.write_debug_ram(2, sh(S1
, S0
, 0));
675 gs
.write_debug_ram(6, data
[0] | (data
[1] << 8));
678 gs
.write_debug_ram(1, lw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 24));
679 gs
.write_debug_ram(2, sw(S1
, S0
, 0));
680 gs
.write_debug_ram(6, data
[0] | (data
[1] << 8) |
681 (data
[2] << 16) | (data
[3] << 24));
684 gs
.write_debug_ram(1, ld(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 24));
685 gs
.write_debug_ram(2, sd(S1
, S0
, 0));
686 gs
.write_debug_ram(6, data
[0] | (data
[1] << 8) |
687 (data
[2] << 16) | (data
[3] << 24));
688 gs
.write_debug_ram(7, data
[4] | (data
[5] << 8) |
689 (data
[6] << 16) | (data
[7] << 24));
692 fprintf(stderr
, "gdbserver error: write %d bytes to 0x%lx -> 0x%lx; "
693 "access_size=%d\n", length
, vaddr
, paddr
, access_size
);
694 gs
.send_packet("E12");
697 gs
.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*3))));
698 gs
.write_debug_ram(4, paddr
);
699 gs
.write_debug_ram(5, paddr
>> 32);
705 if (gs
.read_debug_ram(DEBUG_RAM_SIZE
/ 4 - 1)) {
706 fprintf(stderr
, "Exception happened while writing to 0x%lx -> 0x%lx\n",
710 offset
+= access_size
;
711 if (offset
>= length
) {
712 gs
.send_packet("OK");
715 const unsigned char *d
= data
+ offset
;
716 switch (access_size
) {
718 gs
.write_debug_ram(6, d
[0]);
721 gs
.write_debug_ram(6, d
[0] | (d
[1] << 8));
724 gs
.write_debug_ram(6, d
[0] | (d
[1] << 8) |
725 (d
[2] << 16) | (d
[3] << 24));
728 gs
.write_debug_ram(6, d
[0] | (d
[1] << 8) |
729 (d
[2] << 16) | (d
[3] << 24));
730 gs
.write_debug_ram(7, d
[4] | (d
[5] << 8) |
731 (d
[6] << 16) | (d
[7] << 24));
734 gs
.send_packet("E13");
737 gs
.write_debug_ram(4, paddr
+ offset
);
738 gs
.write_debug_ram(5, (paddr
+ offset
) >> 32);
748 unsigned int access_size
;
749 const unsigned char *data
;
752 class collect_translation_info_op_t
: public operation_t
755 // Read sufficient information from the target into gdbserver structures so
756 // that it's possible to translate vaddr, vaddr+length, and all addresses
757 // in between to physical addresses.
758 collect_translation_info_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, size_t length
) :
759 operation_t(gdbserver
), state(STATE_START
), vaddr(vaddr
), length(length
) {};
761 bool perform_step(unsigned int step
)
763 unsigned int vm
= gs
.virtual_memory();
768 // Nothing to be done.
790 sprintf(buf
, "VM mode %d is not supported by gdbserver.cc.", vm
);
792 return true; // die doesn't return, but gcc doesn't know that.
797 // Perform any reads from the just-completed action.
801 case STATE_READ_SPTBR
:
802 gs
.sptbr
= ((uint64_t) gs
.read_debug_ram(5) << 32) | gs
.read_debug_ram(4);
803 gs
.sptbr_valid
= true;
806 gs
.pte_cache
[pte_addr
] = ((uint64_t) gs
.read_debug_ram(5) << 32) |
807 gs
.read_debug_ram(4);
808 fprintf(stderr
, "pte_cache[0x%lx] = 0x%lx\n", pte_addr
, gs
.pte_cache
[pte_addr
]);
812 // Set up the next action.
813 // We only get here for VM_SV32/39/38.
815 if (!gs
.sptbr_valid
) {
816 state
= STATE_READ_SPTBR
;
817 gs
.write_debug_ram(0, csrr(S0
, CSR_SPTBR
));
818 gs
.write_debug_ram(1, sd(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
819 gs
.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*2))));
824 reg_t base
= gs
.sptbr
<< PGSHIFT
;
825 int ptshift
= (levels
- 1) * ptidxbits
;
826 for (unsigned int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
827 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
829 pte_addr
= base
+ idx
* ptesize
;
830 auto it
= gs
.pte_cache
.find(pte_addr
);
831 if (it
== gs
.pte_cache
.end()) {
832 state
= STATE_READ_PTE
;
834 gs
.write_debug_ram(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
835 gs
.write_debug_ram(1, lw(S1
, S0
, 0));
836 gs
.write_debug_ram(2, sd(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
838 gs
.write_debug_ram(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
839 gs
.write_debug_ram(1, ld(S1
, S0
, 0));
840 gs
.write_debug_ram(2, sd(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
842 gs
.write_debug_ram(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*3))));
843 gs
.write_debug_ram(4, pte_addr
);
844 gs
.write_debug_ram(5, pte_addr
>> 32);
849 reg_t pte
= gs
.pte_cache
[pte_addr
];
850 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
852 if (PTE_TABLE(pte
)) { // next level of page table
853 base
= ppn
<< PGSHIFT
;
855 // We've collected all the data required for the translation.
860 "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%lx\n",
874 unsigned int ptidxbits
;
875 unsigned int ptesize
;
879 ////////////////////////////// gdbserver itself
881 gdbserver_t::gdbserver_t(uint16_t port
, sim_t
*sim
) :
884 recv_buf(64 * 1024), send_buf(64 * 1024)
886 socket_fd
= socket(AF_INET
, SOCK_STREAM
, 0);
887 if (socket_fd
== -1) {
888 fprintf(stderr
, "failed to make socket: %s (%d)\n", strerror(errno
), errno
);
892 fcntl(socket_fd
, F_SETFL
, O_NONBLOCK
);
894 if (setsockopt(socket_fd
, SOL_SOCKET
, SO_REUSEADDR
, &reuseaddr
,
895 sizeof(int)) == -1) {
896 fprintf(stderr
, "failed setsockopt: %s (%d)\n", strerror(errno
), errno
);
900 struct sockaddr_in addr
;
901 memset(&addr
, 0, sizeof(addr
));
902 addr
.sin_family
= AF_INET
;
903 addr
.sin_addr
.s_addr
= INADDR_ANY
;
904 addr
.sin_port
= htons(port
);
906 if (bind(socket_fd
, (struct sockaddr
*) &addr
, sizeof(addr
)) == -1) {
907 fprintf(stderr
, "failed to bind socket: %s (%d)\n", strerror(errno
), errno
);
911 if (listen(socket_fd
, 1) == -1) {
912 fprintf(stderr
, "failed to listen on socket: %s (%d)\n", strerror(errno
), errno
);
917 reg_t
gdbserver_t::translate(reg_t vaddr
)
919 unsigned int vm
= virtual_memory();
920 unsigned int levels
, ptidxbits
, ptesize
;
945 sprintf(buf
, "VM mode %d is not supported by gdbserver.cc.", vm
);
947 return true; // die doesn't return, but gcc doesn't know that.
951 // Handle page tables here. There's a bunch of duplicated code with
952 // collect_translation_info_op_t. :-(
953 reg_t base
= sptbr
<< PGSHIFT
;
954 int ptshift
= (levels
- 1) * ptidxbits
;
955 for (unsigned int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
956 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
958 reg_t pte_addr
= base
+ idx
* ptesize
;
959 auto it
= pte_cache
.find(pte_addr
);
960 if (it
== pte_cache
.end()) {
961 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%lx without first "
962 "collecting the relevant PTEs.\n", vaddr
);
963 die("gdbserver_t::translate()");
966 reg_t pte
= pte_cache
[pte_addr
];
967 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
969 if (PTE_TABLE(pte
)) { // next level of page table
970 base
= ppn
<< PGSHIFT
;
972 // We've collected all the data required for the translation.
973 reg_t vpn
= vaddr
>> PGSHIFT
;
974 reg_t paddr
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
975 paddr
+= vaddr
& (PGSIZE
-1);
976 fprintf(stderr
, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr
, paddr
);
981 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%lx but the relevant "
982 "PTEs are invalid.\n", vaddr
);
983 // TODO: Is it better to throw an exception here?
987 unsigned int gdbserver_t::privilege_mode()
989 unsigned int mode
= get_field(dcsr
, DCSR_PRV
);
990 if (get_field(mstatus
, MSTATUS_MPRV
))
991 mode
= get_field(mstatus
, MSTATUS_MPP
);
995 unsigned int gdbserver_t::virtual_memory()
997 unsigned int mode
= privilege_mode();
1000 return get_field(mstatus
, MSTATUS_VM
);
1003 void gdbserver_t::write_debug_ram(unsigned int index
, uint32_t value
)
1005 sim
->debug_module
.ram_write32(index
, value
);
1008 uint32_t gdbserver_t::read_debug_ram(unsigned int index
)
1010 return sim
->debug_module
.ram_read32(index
);
1013 void gdbserver_t::add_operation(operation_t
* operation
)
1015 operation_queue
.push(operation
);
1018 void gdbserver_t::accept()
1020 client_fd
= ::accept(socket_fd
, NULL
, NULL
);
1021 if (client_fd
== -1) {
1022 if (errno
== EAGAIN
) {
1023 // No client waiting to connect right now.
1025 fprintf(stderr
, "failed to accept on socket: %s (%d)\n", strerror(errno
),
1030 fcntl(client_fd
, F_SETFL
, O_NONBLOCK
);
1033 extended_mode
= false;
1035 // gdb wants the core to be halted when it attaches.
1036 add_operation(new halt_op_t(*this));
1040 void gdbserver_t::read()
1042 // Reading from a non-blocking socket still blocks if there is no data
1045 size_t count
= recv_buf
.contiguous_empty_size();
1047 ssize_t bytes
= ::read(client_fd
, recv_buf
.contiguous_empty(), count
);
1049 if (errno
== EAGAIN
) {
1050 // We'll try again the next call.
1052 fprintf(stderr
, "failed to read on socket: %s (%d)\n", strerror(errno
), errno
);
1055 } else if (bytes
== 0) {
1056 // The remote disconnected.
1058 processor_t
*p
= sim
->get_core(0);
1059 // TODO p->set_halted(false, HR_NONE);
1063 recv_buf
.data_added(bytes
);
1067 void gdbserver_t::write()
1069 if (send_buf
.empty())
1072 while (!send_buf
.empty()) {
1073 unsigned int count
= send_buf
.contiguous_data_size();
1075 ssize_t bytes
= ::write(client_fd
, send_buf
.contiguous_data(), count
);
1077 fprintf(stderr
, "failed to write to socket: %s (%d)\n", strerror(errno
), errno
);
1079 } else if (bytes
== 0) {
1080 // Client can't take any more data right now.
1083 fprintf(stderr
, "wrote %ld bytes: ", bytes
);
1084 for (unsigned int i
= 0; i
< bytes
; i
++) {
1085 fprintf(stderr
, "%c", send_buf
[i
]);
1087 fprintf(stderr
, "\n");
1088 send_buf
.consume(bytes
);
1093 void print_packet(const std::vector
<uint8_t> &packet
)
1095 for (uint8_t c
: packet
) {
1096 if (c
>= ' ' and c
<= '~')
1097 fprintf(stderr
, "%c", c
);
1099 fprintf(stderr
, "\\x%02x", c
);
1101 fprintf(stderr
, "\n");
1104 uint8_t compute_checksum(const std::vector
<uint8_t> &packet
)
1106 uint8_t checksum
= 0;
1107 for (auto i
= packet
.begin() + 1; i
!= packet
.end() - 3; i
++ ) {
1113 uint8_t character_hex_value(uint8_t character
)
1115 if (character
>= '0' && character
<= '9')
1116 return character
- '0';
1117 if (character
>= 'a' && character
<= 'f')
1118 return 10 + character
- 'a';
1119 if (character
>= 'A' && character
<= 'F')
1120 return 10 + character
- 'A';
1124 uint8_t extract_checksum(const std::vector
<uint8_t> &packet
)
1126 return character_hex_value(*(packet
.end() - 1)) +
1127 16 * character_hex_value(*(packet
.end() - 2));
1130 void gdbserver_t::process_requests()
1132 // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1134 while (!recv_buf
.empty()) {
1135 std::vector
<uint8_t> packet
;
1136 for (unsigned int i
= 0; i
< recv_buf
.size(); i
++) {
1137 uint8_t b
= recv_buf
[i
];
1139 if (packet
.empty() && expect_ack
&& b
== '+') {
1140 recv_buf
.consume(1);
1144 if (packet
.empty() && b
== 3) {
1145 fprintf(stderr
, "Received interrupt\n");
1146 recv_buf
.consume(1);
1152 // Start of new packet.
1153 if (!packet
.empty()) {
1154 fprintf(stderr
, "Received malformed %ld-byte packet from debug client: ",
1156 print_packet(packet
);
1157 recv_buf
.consume(i
);
1162 packet
.push_back(b
);
1164 // Packets consist of $<packet-data>#<checksum>
1165 // where <checksum> is
1166 if (packet
.size() >= 4 &&
1167 packet
[packet
.size()-3] == '#') {
1168 handle_packet(packet
);
1169 recv_buf
.consume(i
+1);
1173 // There's a partial packet in the buffer. Wait until we get more data to
1175 if (packet
.size()) {
1181 void gdbserver_t::handle_halt_reason(const std::vector
<uint8_t> &packet
)
1186 void gdbserver_t::handle_general_registers_read(const std::vector
<uint8_t> &packet
)
1188 add_operation(new general_registers_read_op_t(*this));
1191 void gdbserver_t::set_interrupt(uint32_t hartid
) {
1192 sim
->debug_module
.set_interrupt(hartid
);
1195 // First byte is the most-significant one.
1196 // Eg. "08675309" becomes 0x08675309.
1197 uint64_t consume_hex_number(std::vector
<uint8_t>::const_iterator
&iter
,
1198 std::vector
<uint8_t>::const_iterator end
)
1202 while (iter
!= end
) {
1204 uint64_t c_value
= character_hex_value(c
);
1214 // First byte is the least-significant one.
1215 // Eg. "08675309" becomes 0x09536708
1216 uint64_t consume_hex_number_le(std::vector
<uint8_t>::const_iterator
&iter
,
1217 std::vector
<uint8_t>::const_iterator end
)
1220 unsigned int shift
= 4;
1222 while (iter
!= end
) {
1224 uint64_t c_value
= character_hex_value(c
);
1228 value
|= c_value
<< shift
;
1229 if ((shift
% 8) == 0)
1237 void consume_string(std::string
&str
, std::vector
<uint8_t>::const_iterator
&iter
,
1238 std::vector
<uint8_t>::const_iterator end
, uint8_t separator
)
1240 while (iter
!= end
&& *iter
!= separator
) {
1241 str
.append(1, (char) *iter
);
1246 void gdbserver_t::handle_register_read(const std::vector
<uint8_t> &packet
)
1250 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1251 unsigned int n
= consume_hex_number(iter
, packet
.end());
1253 return send_packet("E01");
1255 add_operation(new register_read_op_t(*this, n
));
1258 void gdbserver_t::handle_register_write(const std::vector
<uint8_t> &packet
)
1262 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1263 unsigned int n
= consume_hex_number(iter
, packet
.end());
1265 return send_packet("E05");
1268 reg_t value
= consume_hex_number_le(iter
, packet
.end());
1270 return send_packet("E06");
1272 processor_t
*p
= sim
->get_core(0);
1274 add_operation(new register_write_op_t(*this, n
, value
));
1276 return send_packet("OK");
1279 void gdbserver_t::handle_memory_read(const std::vector
<uint8_t> &packet
)
1282 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1283 reg_t address
= consume_hex_number(iter
, packet
.end());
1285 return send_packet("E10");
1287 reg_t length
= consume_hex_number(iter
, packet
.end());
1289 return send_packet("E11");
1291 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1292 add_operation(new memory_read_op_t(*this, address
, length
));
1295 void gdbserver_t::handle_memory_binary_write(const std::vector
<uint8_t> &packet
)
1297 // X addr,length:XX...
1298 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1299 reg_t address
= consume_hex_number(iter
, packet
.end());
1301 return send_packet("E20");
1303 reg_t length
= consume_hex_number(iter
, packet
.end());
1305 return send_packet("E21");
1309 return send_packet("OK");
1312 unsigned char *data
= new unsigned char[length
];
1313 for (unsigned int i
= 0; i
< length
; i
++) {
1314 if (iter
== packet
.end()) {
1315 return send_packet("E22");
1320 // The binary data representation uses 7d (ascii ‘}’) as an escape
1321 // character. Any escaped byte is transmitted as the escape character
1322 // followed by the original character XORed with 0x20. For example, the
1323 // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1324 // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1326 if (iter
== packet
.end()) {
1327 return send_packet("E23");
1335 return send_packet("E4b"); // EOVERFLOW
1337 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1338 add_operation(new memory_write_op_t(*this, address
, length
, data
));
1341 void gdbserver_t::handle_continue(const std::vector
<uint8_t> &packet
)
1344 processor_t
*p
= sim
->get_core(0);
1345 if (packet
[2] != '#') {
1346 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1347 dpc
= consume_hex_number(iter
, packet
.end());
1349 return send_packet("E30");
1352 add_operation(new continue_op_t(*this, false));
1355 void gdbserver_t::handle_step(const std::vector
<uint8_t> &packet
)
1358 if (packet
[2] != '#') {
1359 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1361 //p->state.pc = consume_hex_number(iter, packet.end());
1363 return send_packet("E40");
1366 add_operation(new continue_op_t(*this, true));
1369 void gdbserver_t::handle_kill(const std::vector
<uint8_t> &packet
)
1372 // The exact effect of this packet is not specified.
1373 // Looks like OpenOCD disconnects?
1377 void gdbserver_t::handle_extended(const std::vector
<uint8_t> &packet
)
1379 // Enable extended mode. In extended mode, the remote server is made
1380 // persistent. The ‘R’ packet is used to restart the program being debugged.
1382 extended_mode
= true;
1385 void gdbserver_t::handle_breakpoint(const std::vector
<uint8_t> &packet
)
1387 // insert: Z type,addr,kind
1388 // remove: z type,addr,kind
1390 software_breakpoint_t bp
;
1391 bool insert
= (packet
[1] == 'Z');
1392 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1393 int type
= consume_hex_number(iter
, packet
.end());
1395 return send_packet("E50");
1397 bp
.address
= consume_hex_number(iter
, packet
.end());
1399 return send_packet("E51");
1401 bp
.size
= consume_hex_number(iter
, packet
.end());
1402 // There may be more options after a ; here, but we don't support that.
1404 return send_packet("E52");
1406 if (bp
.size
!= 2 && bp
.size
!= 4) {
1407 return send_packet("E53");
1410 fence_i_required
= true;
1411 add_operation(new collect_translation_info_op_t(*this, bp
.address
, bp
.size
));
1413 unsigned char* swbp
= new unsigned char[4];
1415 swbp
[0] = C_EBREAK
& 0xff;
1416 swbp
[1] = (C_EBREAK
>> 8) & 0xff;
1418 swbp
[0] = EBREAK
& 0xff;
1419 swbp
[1] = (EBREAK
>> 8) & 0xff;
1420 swbp
[2] = (EBREAK
>> 16) & 0xff;
1421 swbp
[3] = (EBREAK
>> 24) & 0xff;
1424 breakpoints
[bp
.address
] = new software_breakpoint_t(bp
);
1425 add_operation(new memory_read_op_t(*this, bp
.address
, bp
.size
,
1426 breakpoints
[bp
.address
]->instruction
));
1427 add_operation(new memory_write_op_t(*this, bp
.address
, bp
.size
, swbp
));
1430 software_breakpoint_t
*found_bp
;
1431 found_bp
= breakpoints
[bp
.address
];
1432 unsigned char* instruction
= new unsigned char[4];
1433 memcpy(instruction
, found_bp
->instruction
, 4);
1434 add_operation(new memory_write_op_t(*this, found_bp
->address
,
1435 found_bp
->size
, instruction
));
1436 breakpoints
.erase(bp
.address
);
1440 return send_packet("OK");
1443 void gdbserver_t::handle_query(const std::vector
<uint8_t> &packet
)
1446 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1448 consume_string(name
, iter
, packet
.end(), ':');
1449 if (iter
!= packet
.end())
1451 if (name
== "Supported") {
1453 while (iter
!= packet
.end()) {
1454 std::string feature
;
1455 consume_string(feature
, iter
, packet
.end(), ';');
1456 if (iter
!= packet
.end())
1458 if (feature
== "swbreak+") {
1462 send("PacketSize=131072;");
1463 return end_packet();
1466 fprintf(stderr
, "Unsupported query %s\n", name
.c_str());
1467 return send_packet("");
1470 void gdbserver_t::handle_packet(const std::vector
<uint8_t> &packet
)
1472 if (compute_checksum(packet
) != extract_checksum(packet
)) {
1473 fprintf(stderr
, "Received %ld-byte packet with invalid checksum\n", packet
.size());
1474 fprintf(stderr
, "Computed checksum: %x\n", compute_checksum(packet
));
1475 print_packet(packet
);
1480 fprintf(stderr
, "Received %ld-byte packet from debug client: ", packet
.size());
1481 print_packet(packet
);
1484 switch (packet
[1]) {
1486 return handle_extended(packet
);
1488 return handle_halt_reason(packet
);
1490 return handle_general_registers_read(packet
);
1492 // return handle_kill(packet);
1494 return handle_memory_read(packet
);
1496 // return handle_memory_write(packet);
1498 return handle_memory_binary_write(packet
);
1500 return handle_register_read(packet
);
1502 return handle_register_write(packet
);
1504 return handle_continue(packet
);
1506 return handle_step(packet
);
1509 return handle_breakpoint(packet
);
1512 return handle_query(packet
);
1516 fprintf(stderr
, "** Unsupported packet: ");
1517 print_packet(packet
);
1521 void gdbserver_t::handle_interrupt()
1523 processor_t
*p
= sim
->get_core(0);
1524 add_operation(new halt_op_t(*this, true));
1527 void gdbserver_t::handle()
1529 if (client_fd
> 0) {
1530 processor_t
*p
= sim
->get_core(0);
1532 bool interrupt
= sim
->debug_module
.get_interrupt(0);
1534 if (!interrupt
&& !operation_queue
.empty()) {
1535 operation_t
*operation
= operation_queue
.front();
1536 if (operation
->step()) {
1537 operation_queue
.pop();
1542 bool halt_notification
= sim
->debug_module
.get_halt_notification(0);
1543 if (halt_notification
) {
1544 sim
->debug_module
.clear_halt_notification(0);
1545 add_operation(new halt_op_t(*this, true));
1555 if (operation_queue
.empty()) {
1556 this->process_requests();
1560 void gdbserver_t::send(const char* msg
)
1562 unsigned int length
= strlen(msg
);
1563 for (const char *c
= msg
; *c
; c
++)
1564 running_checksum
+= *c
;
1565 send_buf
.append((const uint8_t *) msg
, length
);
1568 void gdbserver_t::send(uint64_t value
)
1571 for (unsigned int i
= 0; i
< 8; i
++) {
1572 sprintf(buffer
, "%02x", (int) (value
& 0xff));
1578 void gdbserver_t::send(uint32_t value
)
1581 for (unsigned int i
= 0; i
< 4; i
++) {
1582 sprintf(buffer
, "%02x", (int) (value
& 0xff));
1588 void gdbserver_t::send_packet(const char* data
)
1596 void gdbserver_t::start_packet()
1599 running_checksum
= 0;
1602 void gdbserver_t::end_packet(const char* data
)
1608 char checksum_string
[4];
1609 sprintf(checksum_string
, "#%02x", running_checksum
);
1610 send(checksum_string
);