riscv/htif.cc

   1 #include "htif.h"
   2 #include "common.h"
   3 #include "sim.h"
   4 #include <unistd.h>
   5 #include <stdexcept>
   6 #include <stdlib.h>
   7 #include <errno.h>
   8 #include <assert.h>
   9 #include <stddef.h>
  10 #include <poll.h>
  11
  12 htif_isasim_t::htif_isasim_t(sim_t* _sim, const std::vector<std::string>& args)
  13   : htif_pthread_t(args), sim(_sim), reset(true), seqno(1)
  14 {
  15 }
  16
  17 void htif_isasim_t::tick()
  18 {
  19   do tick_once(); while (reset);
  20 }
  21
  22 void htif_isasim_t::tick_once()
  23 {
  24   packet_header_t hdr;
  25   recv(&hdr, sizeof(hdr));
  26
  27   char buf[hdr.get_packet_size()];
  28   memcpy(buf, &hdr, sizeof(hdr));
  29   recv(buf + sizeof(hdr), hdr.get_payload_size());
  30   packet_t p(buf);
  31
  32   assert(hdr.seqno == seqno);
  33
  34   switch (hdr.cmd)
  35   {
  36     case HTIF_CMD_READ_MEM:
  37     {
  38       packet_header_t ack(HTIF_CMD_ACK, seqno, hdr.data_size, 0);
  39       send(&ack, sizeof(ack));
  40
  41       uint64_t buf[hdr.data_size];
  42       for (size_t i = 0; i < hdr.data_size; i++)
  43         buf[i] = sim->mmu->load_uint64((hdr.addr+i)*HTIF_DATA_ALIGN);
  44       send(buf, hdr.data_size * sizeof(buf[0]));
  45       break;
  46     }
  47     case HTIF_CMD_WRITE_MEM:
  48     {
  49       const uint64_t* buf = (const uint64_t*)p.get_payload();
  50       for (size_t i = 0; i < hdr.data_size; i++)
  51         sim->mmu->store_uint64((hdr.addr+i)*HTIF_DATA_ALIGN, buf[i]);
  52
  53       packet_header_t ack(HTIF_CMD_ACK, seqno, 0, 0);
  54       send(&ack, sizeof(ack));
  55       break;
  56     }
  57     case HTIF_CMD_READ_CONTROL_REG:
  58     case HTIF_CMD_WRITE_CONTROL_REG:
  59     {
  60       reg_t coreid = hdr.addr >> 20;
  61       reg_t regno = hdr.addr & ((1<<20)-1);
  62       assert(hdr.data_size == 1);
  63
  64       packet_header_t ack(HTIF_CMD_ACK, seqno, 1, 0);
  65       send(&ack, sizeof(ack));
  66
  67       if (coreid == 0xFFFFF) // system control register space
  68       {
  69         uint64_t pcr = sim->get_scr(regno);
  70         send(&pcr, sizeof(pcr));
  71         break;
  72       }
  73
  74       assert(coreid < sim->num_cores());
  75       uint64_t pcr = sim->procs[coreid]->get_pcr(regno);
  76       send(&pcr, sizeof(pcr));
  77
  78       if (regno == PCR_TOHOST)
  79           sim->procs[coreid]->tohost = 0;
  80
  81       if (hdr.cmd == HTIF_CMD_WRITE_CONTROL_REG)
  82       {
  83         uint64_t val;
  84         memcpy(&val, p.get_payload(), sizeof(val));
  85         if (regno == PCR_RESET)
  86         {
  87           reset = val & 1;
  88           sim->procs[coreid]->reset(reset);
  89         }
  90         else
  91         {
  92           sim->procs[coreid]->set_pcr(regno, val);
  93         }
  94       }
  95       break;
  96     }
  97     default:
  98       abort();
  99   }
 100   seqno++;
 101 }
 102
 103 void htif_isasim_t::stop()
 104 {
 105   htif_t::stop();
 106   exit(exit_code());
 107 }