rename sv vlen to sv voffs, add csr and reg tables
[riscv-isa-sim.git] / riscv / insn_template.cc
1 // See LICENSE for license details.
2
3 #include "insn_template.h"
4
5 #ifdef SPIKE_SIMPLEV
6 #include "sv_decode.h"
7 #endif
8
9 reg_t rv32_NAME(processor_t* p, insn_t s_insn, reg_t pc)
10 {
11 int xlen = 32;
12 reg_t npc = sext_xlen(pc + insn_length(OPCODE));
13 insn_bits_t bits = s_insn.bits();
14 #ifdef SPIKE_SIMPLEV
15 int voffs = 0;
16 sv_insn_t insn(bits, voffs);
17 #include "insns/NAME.h"
18 trace_opcode(p, OPCODE, s_insn);
19 #else
20 insn_t insn(bits);
21 #include "insns/NAME.h"
22 trace_opcode(p, OPCODE, s_insn);
23 #endif
24 return npc;
25 }
26
27 reg_t rv64_NAME(processor_t* p, insn_t s_insn, reg_t pc)
28 {
29 int xlen = 64;
30 reg_t npc = sext_xlen(pc + insn_length(OPCODE));
31 insn_bits_t bits = s_insn.bits();
32 #ifdef SPIKE_SIMPLEV
33 int voffs = 0;
34 sv_insn_t insn(bits, voffs);
35 #include "insns/NAME.h"
36 trace_opcode(p, OPCODE, s_insn);
37 #else
38 insn_t insn(bits);
39 #include "insns/NAME.h"
40 trace_opcode(p, OPCODE, s_insn);
41 #endif
42 return npc;
43 }