1 // See LICENSE for license details.
3 reg_t
FN(processor_t
* p
, insn_t s_insn
, reg_t pc
)
6 reg_t npc
= sext_xlen(pc
+ insn_length(INSNCODE
));
7 // messy way to do it: insn_t is used elsewhere in a union,
8 // so a workaround is to grab the bits from the insn_t
9 // and create an sv-variant. also an opportunity to pass
10 // in the loop index (voffs) which will be added on to
11 // any registers that are marked as "vectorised"
12 insn_bits_t bits
= s_insn
.bits();
16 sv_insn_t
insn(bits
, voffs
);
17 bool vectorop
= false;
19 // identify which regs have had their CSR entries set as vectorised.
20 // really could do with a macro for-loop here... oh well...
21 // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
23 vectorop
&= check_reg(true, s_insn
.rd());
26 vectorop
&= check_reg(true, s_insn
.rs1());
29 vectorop
&= check_reg(true, s_insn
.rs2());
32 vectorop
&= check_reg(true, s_insn
.rs3());
34 // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb)
36 vectorop
&= check_reg(false, s_insn
.frd());
39 vectorop
&= check_reg(false, s_insn
.frs1());
42 vectorop
&= check_reg(false, s_insn
.rs2());
45 vectorop
&= check_reg(false, s_insn
.rs3());
48 // if vectorop is set, one of the regs is not a scalar,
49 // so we must read the VL CSR and do a loop
52 // TODO: vlen = p->CSR(SIMPLEV_VL); // something like that...
54 for (; voffs
< vlen
; voffs
++)
62 trace_opcode(p
, INSNCODE
, insn
);