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Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git] / riscv / insns / amoadd_w.h
1 require_extension('A');
2 WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs + RS2; })));
Simple-V augmented version of spike