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[xcc, sim] changed instruction format so imm12 subs for rs2
[riscv-isa-sim.git]
/
riscv
/
insns
/
amow_or.h
1
reg_t v
=
mmu
.
load_int32
(
RS1
);
2
mmu
.
store_uint32
(
RS1
,
RS2
|
v
);
3
RDR
=
v
;