projects / riscv-isa-sim.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
[sim] add while to interactive_until
[riscv-isa-sim.git] / riscv / insns / ble.h
1 if(sreg_t(cmp_trunc(RA)) <= sreg_t(cmp_trunc(RB)))
2 npc = BRANCH_TARGET;
Simple-V augmented version of spike