projects / riscv-isa-sim.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git] / riscv / insns / blt.h
1 if(sreg_t(RS1) < sreg_t(RS2))
2 set_pc(BRANCH_TARGET);
Simple-V augmented version of spike