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HEAD
New RV64C proposal
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_add.h
1
require_extension
(
'C'
);
2
require
(
insn
.
rvc_rs2
() !=
0
);
3
if
(
insn
.
rvc_rd
() ==
0
) {
// c.ebreak
4
throw
trap_breakpoint
();
5
}
else
{
6
WRITE_RD
(
sext_xlen
(
RVC_RS1
+
RVC_RS2
));
7
}