Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / c_addi4spn.h

require_extension('C');
require(insn.rvc_addi4spn_imm() != 0);
WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm()));