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HEAD
Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_bnez.h
1
require_extension
(
'C'
);
2
if
(
RVC_RS1S
!=
0
)
3
set_pc
(
pc
+
insn
.
rvc_b_imm
());