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[xcc,sim,opcodes] added more RVC instructions
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_flw.h
1
require_rvc
;
2
require_fp
;
3
FCRDS
=
mmu
.
load_int32
(
CRS1S
+
CIMM5
*
4
);