Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / c_jalr.h

require_extension('C');
require(insn.rvc_rs1() != 0);
reg_t tmp = npc;
set_pc(RVC_RS1 & ~reg_t(1));
WRITE_REG(X_RA, tmp);