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C.LWSP and C.LDSP with rd=0 are legal instructions
[riscv-isa-sim.git] / riscv / insns / c_lwsp.h
1 require_extension('C');
2 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
Simple-V augmented version of spike