projects / riscv-isa-sim.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git] / riscv / insns / c_mv.h
1 require_extension('C');
2 require(insn.rvc_rs2() != 0);
3 WRITE_RD(RVC_RS2);
Simple-V augmented version of spike