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HEAD
Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded...
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_srli.h
1
require_extension
(
'C'
);
2
require
(
insn
.
rvc_zimm
() <
xlen
&&
insn
.
rvc_zimm
() >
0
);
3
WRITE_RVC_RS1S
(
sext_xlen
(
zext_xlen
(
RVC_RS1S
) >>
insn
.
rvc_zimm
()));