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HEAD
Use WRITE_RD/WRITE_FRD macros to write registers
[riscv-isa-sim.git]
/
riscv
/
insns
/
divw.h
1
require_xpr64
;
2
sreg_t lhs
=
sext32
(
RS1
);
3
sreg_t rhs
=
sext32
(
RS2
);
4
if
(
rhs
==
0
)
5
WRITE_RD
(
UINT64_MAX
);
6
else
7
WRITE_RD
(
sext32
(
lhs
/
rhs
));