Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fcvt_lu_d.h

require_extension('D');
require_rv64;
require_fp;
softfloat_roundingMode = RM;
WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
set_fp_exceptions;