Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / fdiv_q.h

require_extension('Q');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f128_div(f128(FRS1), f128(FRS2)));
set_fp_exceptions;